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DM9602N Fiches technique(PDF) 1 Page - Fairchild Semiconductor |
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DM9602N Fiches technique(HTML) 1 Page - Fairchild Semiconductor |
1 / 6 page © 2000 Fairchild Semiconductor Corporation DS006611 www.fairchildsemi.com August 1986 Revised February 2000 DM9602 Dual Retriggerable, Resettable One Shots General Description These dual resettable, retriggerable one shots have two inputs per function; one which is active HIGH, and one which is active LOW. This allows the designer to employ either leading-edge or trailing-edge triggering, which is independent of input transition times. When input condi- tions for triggering are met, a new cycle starts and the external capacitor is allowed to rapidly discharge and then charge again. The retriggerable feature permits output pulse widths to be extended. In fact a continuous true out- put can be maintained by having an input cycle time which is shorter than the output cycle time. The output pulse may then be terminated at any time by applying a LOW logic level to the RESET pin. Retriggering may be inhibited by either connecting the Q output to an active HIGH input, or the Q output to an active LOW input. Features s 70 ns to ∞ output width range s Resettable and retriggerable—0% to 100% duty cycle s TTL input gating—leading or trailing edge triggering s Complementary TTL outputs s Optional retrigger lock-out capability s Pulse width compensated for VCC and temperature vari- ations Ordering Code: Connection Diagram Function Table H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Logic Diagrams Order Number Package Number Package Description DM9602N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Pin Numbers Operation AB CLR H →L L H Trigger HL →H H Trigger XX L Reset |
Numéro de pièce similaire - DM9602N |
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Description similaire - DM9602N |
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