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DM74AS651 Fiches technique(PDF) 5 Page - Fairchild Semiconductor |
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DM74AS651 Fiches technique(HTML) 5 Page - Fairchild Semiconductor |
5 / 8 page 5 www.fairchildsemi.com DM74AS651 Switching Characteristics Note 4: These parameters are measured with the internal output state of the storage register opposite to that of the bus input. Symbol Parameter Conditions From To Min Max Units fMAX Maximum Clock Frequency VCC = 4.5V to 5.5V 90 MHz tPLH Propagation Delay Time R1 = R2 = 500Ω 28.5 ns LOW-to-HIGH Level Output CL = 50 pF CBA or CAB A or B tPHL Propagation Delay Time 29 ns HIGH-to-LOW Level Output tPLH Propagation Delay Time 28 ns LOW-to-HIGH Level Output A or B B or A tPHL Propagation Delay Time 17 ns HIGH-to-LOW Level Output tPLH Propagation Delay Time 211 ns LOW-to-HIGH Level Output SBA or SAB A or B tPHL Propagation Delay Time (Note 4) 29 ns HIGH-to-LOW Level Output tPZH Output Enable Time 210 ns to HIGH Level Output tPZL Output Enable Time 316 ns to LOW Level Output Enable GBA A tPHZ Output Disable Time 29 ns from HIGH Level Output tPLZ Output Disable Time 29 ns from LOW Level Output tPZH Output Disable Time 311 ns to HIGH Level Output tPZL Output Disable Time 316 ns to LOW Level Output Enable GAB B tPHZ Output Disable Time 210 ns from HIGH Level Output tPLZ Output Disable Time 211 ns from LOW Level Output |
Numéro de pièce similaire - DM74AS651 |
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Description similaire - DM74AS651 |
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