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MPC948 Fiches technique(PDF) 3 Page - Motorola, Inc |
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MPC948 Fiches technique(HTML) 3 Page - Motorola, Inc |
3 / 6 page MPC948 TIMING SOLUTIONS BR1333 — Rev 6 3 MOTOROLA ABSOLUTE MAXIMUM RATINGS* Symbol Parameter Min Max Unit VCC Supply Voltage –0.3 4.6 V VI Input Voltage –0.3 VDD + 0.3 V IIN Input Current ±20 mA TStor Storage Temperature Range –40 125 °C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied. DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±0.3V) Symbol Characteristic Min Typ Max Unit Condition VIH Input HIGH Voltage PECL_CLK Other 2.135 2.0 2.42 3.60 V Single Ended Spec VIL Input LOW Voltage PECL_CLK Other 1.49 1.825 0.8 V Single Ended Spec VPP Peak–to–Peak Input Voltage PECL_CLK 300 1000 mV VCMR Common Mode Range PECL_CLK VCC – 2.0 VCC – 0.6 V Note NO TAG VOH Output HIGH Voltage 2.5 V IOH = –20mA (Note NO TAG) VOL Output LOW Voltage 0.4 V IOL = 20mA (Note NO TAG) IIN Input Current ±100 µA Note NO TAG CIN Input Capacitance 4 pF Cpd Power Dissipation Capacitance 25 pF Per Output ICC Maximum Quiescent Supply Current 22 30 mA 1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “HIGH” input is within the VCMR range and the input swing lies within the VPP specification. 2. The MPC948 outputs can drive series or parallel terminated 50 Ω (or 50Ω to VCC/2) transmission lines on the incident edge (see Applications Info section). 3. Inputs have pull–up resistors which affect input current, PECL_CLK has a pull–down resistor. AC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±0.3V) Symbol Characteristic Min Typ Max Unit Condition Fmax Maximum Input Frequency 150 MHz Note NO TAG tpd Propagation Delay PECL_CLK to Q TTL_CLK to Q 4.0 4.4 8.0 8.9 ns Note NO TAG tsk(o) Output–to–Output Skew 350 ps Note NO TAG tsk(pr) Part–to–Part Skew PECL_CLK to Q TTL_CLK to Q 1.5 2.0 ns Notes NO TAG, NO TAG tpwo Output Pulse Width tCYCLE/2– 800 tCYCLE/2+ 800 ps Notes NO TAG, NO TAG Measured at VCC/2 ts Setup Time Sync_OE to PECL_CLK Sync_OE to TTL_CLK 1.0 0.0 ns Notes NO TAG, NO TAG th Hold Time PECL_CLK to Sync_OE TTL_CLK to Sync_OE 0.0 1.0 ns Notes NO TAG, NO TAG tPZL,tPZH Output Enable Time 3 11 ns tPLZ,tPHZ Output Disable Time 3 11 ns tr, tf Output Rise/Fall Time 0.20 1.0 ns 0.8V to 2.0V 4. Driving 50 Ω transmission lines 5. Part–to–part skew at a given temperature and voltage 6. Assumes 50% input duty cycle. 7. Setup and Hold times are relative to the falling edge of the input clock |
Numéro de pièce similaire - MPC948 |
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Description similaire - MPC948 |
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