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74VHC245NX Fiches technique(PDF) 1 Page - Fairchild Semiconductor |
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74VHC245NX Fiches technique(HTML) 1 Page - Fairchild Semiconductor |
1 / 7 page © 2005 Fairchild Semiconductor Corporation DS011520 www.fairchildsemi.com November 1992 Revised April 2005 74VHC245 Octal Bidirectional Transceiver with 3-STATE Outputs General Description The VHC245 is an advanced high speed CMOS octal bus transceiver fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipo- lar Schottky TTL while maintaining the CMOS low power dissipation. The VHC245 is intended for bidirectional asyn- chronous communication between data busses. The direc- tion of data transmission is determined by the level of the T/R input. The enable input can be used to disable the device so that the busses are effectively isolated. All inputs are equipped with protection circuits against static dis- charge. Features s High Speed: tPD 4.0 ns (typ) at VCC 5V s High Noise Immunity: VNIH VNIL 28% VCC (Min) s Power Down Protection is provided on all inputs s Low Noise: VOLP 0.9V (typ) s Low Power Dissipation: ICC 4 PA (Max) @ TA 25qC s Pin and Function Compatible with 74HC245 Ordering Code: Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Logic Symbol IEEE/IEC Pin Description Connection Diagram Truth Table H HIGH Voltage Level L LOW Voltage Level X Immaterial Any unused bus terminals during HIGH-Z State must be held HIGH or LOW. Order Number Package Number Package Description 74VHC245M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74VHC245SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC245MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC245N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Pin Description Names OE Output Enable Input T/R Transmit/Receive Input A0–A7 Side A Inputs or 3-STATE Outputs B0–B7 Side B Inputs or 3-STATE Outputs Inputs Outputs OE T/R L L Bus B Data to Bus A L H Bus A Data to Bus B H X HIGH-Z State |
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