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74LVX138SJX Fiches technique(PDF) 1 Page - Fairchild Semiconductor |
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74LVX138SJX Fiches technique(HTML) 1 Page - Fairchild Semiconductor |
1 / 7 page © 2003 Fairchild Semiconductor Corporation DS011615 www.fairchildsemi.com June 1993 Revised October 2003 74LVX138 Low Voltage 1-of-8 Decoder/Demultiplexer General Description The LVX138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three LVX138 devices or a 1-of-32 decoder using four LVX138 devices and one inverter. Features s Input voltage level translation from 5V to 3V s Ideal for low power/low noise 3.3V applications s Guaranteed simultaneous switching noise level and dynamic threshold performance Ordering Code: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram Pin Descriptions Order Number Package Number Package Description 74LVX138M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LVX138SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVX138MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pin Names Description A0–A2 Address Inputs E1– E2 Enable Inputs E3 Enable Input O0–O7 Outputs |
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