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74LVTH16501MTD Fiches technique(PDF) 2 Page - Fairchild Semiconductor |
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74LVTH16501MTD Fiches technique(HTML) 2 Page - Fairchild Semiconductor |
2 / 7 page www.fairchildsemi.com 2 Connection Diagram Pin Descriptions Function Table (Note 1) H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance ↑ = LOW-to-HIGH Clock Transition Note 1: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, and CLKBA. OEBA is active LOW Note 2: Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. Note 3: Output level before the indicated steady-state input conditions were established. Functional Description For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/ flip-flop on the LOW-to-HIGH transition of CLKAB. Output- enable OEAB is active-HIGH. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A-to-B but uses OEBA, LEBA, and CLKBA. The output enables are com- plementary (OEAB is active-HIGH and OEBA is active- LOW). Logic Diagram Pin Names Description A1–A18 Data Register A Inputs/3-STATE Outputs B1–B18 Data Register B Inputs/3-STATE Outputs CLKAB, CLKBA Clock Pulse Inputs LEAB, LEBA Latch Enable Inputs OEAB, OEBA Output Enable Inputs Inputs Output OEAB LEAB CLKAB An Bn L XXX Z HH X L L HH X H H HL ↑ LL HL ↑ HH HL H X B0 (Note 2) HL L X B0 (Note 3) |
Numéro de pièce similaire - 74LVTH16501MTD |
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Description similaire - 74LVTH16501MTD |
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