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74ACT823SPC Fiches technique(PDF) 2 Page - Fairchild Semiconductor |
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74ACT823SPC Fiches technique(HTML) 2 Page - Fairchild Semiconductor |
2 / 7 page www.fairchildsemi.com 2 Functional Description The ACT823 consists of nine D-type edge-triggered flip- flops. These have 3-STATE outputs for bus systems orga- nized with inputs and outputs on opposite sides. The buff- ered clock (CP) and buffered Output Enable (OE) are common to all flip-flops. The flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. With OE LOW, the contents of the flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. In addition to the Clock and Out- put Enable pins, there are Clear (CLR) and Clock Enable (EN) pins. These devices are ideal for parity bus interfacing in high performance systems. When CLR is LOW and OE is LOW, the outputs are LOW. When CLR is HIGH, data can be entered into the flip-flops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When the EN is HIGH, the outputs do not change state, regardless of the data or clock input transitions. Function Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition NC = No Change Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Inputs Internal Output Function OE CLR EN CP D Q O HX L L L Z High Z HX L H H Z High Z H L X X X L Z Clear L L X X X L L Clear HHH X X NC Z Hold LH H X X NC NC Hold HH L LL Z Load HH L HH Z Load LH L LL L Load LH L HH H Load |
Numéro de pièce similaire - 74ACT823SPC |
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Description similaire - 74ACT823SPC |
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