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74HC240-Q100 Fiches technique(PDF) 9 Page - NXP Semiconductors |
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74HC240-Q100 Fiches technique(HTML) 9 Page - NXP Semiconductors |
9 / 16 page 74HC_HCT240_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 1 — 30 July 2012 9 of 16 NXP Semiconductors 74HC240-Q100; 74HCT240-Q100 Octal buffer/line driver; 3-state; inverting Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 8. Test circuit for measuring switching times VM VM tW tW 10 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % tf tr tr tf 001aad983 DUT VCC VCC VI VO RT RL S1 CL open G Table 9. Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74HC240-Q100 VCC 6ns 15pF, 50 pF 1k open GND VCC 74HCT240-Q100 3 V 6 ns 15 pF, 50 pF 1 k open GND VCC |
Numéro de pièce similaire - 74HC240-Q100 |
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Description similaire - 74HC240-Q100 |
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