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74ABT16646CSSC Fiches technique(PDF) 1 Page - Fairchild Semiconductor |
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74ABT16646CSSC Fiches technique(HTML) 1 Page - Fairchild Semiconductor |
1 / 9 page © 1999 Fairchild Semiconductor Corporation DS011644 www.fairchildsemi.com October 1993 Revised November 1999 74ABT16646 16-Bit Transceivers and Registers with 3-STATE Outputs General Description The ABT16646 consists of bus transceiver circuits with 3- STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. Control OE and direction pins are pro- vided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or the B register or in both. The select controls can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when the enable control OE is Active LOW. In the isolation mode (control OE HIGH), A data may be stored in the B register and/or B data may be stored in the A register. Features s Independent registers for A and B buses s Multiplexed real-time and stored data s A and B output sink capability of 64 mA, source capability of 32 mA s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Nondestructive hot insertion capability Ordering Code: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Connection Diagram Order Number Package Number Package Description 74ABT16646CSSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide 74ABT16646CMTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Pin Names Description A0–A15 Data Register A Inputs/ 3-STATE Outputs B0–B15 Data Register B Inputs/ 3-STATE Outputs CPABn, CPBAn Clock Pulse Inputs SABn, SBAn Select Inputs OEn Output Enable Input DIR Direction Control Input |
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