ADV7182 datasheet(7/96 Pages) AD

No de pièce	ADV7182

Description	10-Bit, SDTV Video Decoder with Differential Inputs

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Fabricant	AD [Analog Devices]

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Data Sheet

ADV7182

Rev. A | Page 7 of 96

TIMING SPECIFICATIONS

Guaranteed by characterization. AVDD, DVDD, and PVDD = 1.71 V to 1.89 V; DVDDIO = 1.71 V to 3.46 V, specified at operating temperature

range, unless otherwise noted.

Table 4.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

SYSTEM CLOCK AND CRYSTAL

Nominal Frequency

28.63636

MHz

Frequency Stability

±50

ppm

I2C PORT

SCLK Frequency

400

kHz

SCLK Minimum Pulse Width High

t1

0.6

μs

SCLK Minimum Pulse Width Low

t2

1.3

μs

Hold Time (Start Condition)

t3

0.6

μs

Setup Time (Start Condition)

t4

0.6

μs

SDATA Setup Time

t5

100

ns

SCLK and SDATA Rise Times

t6

300

ns

SCLK and SDATA Fall Times

t7

300

ns

Setup Time for Stop Condition

t8

0.6

μs

RESET FEATURE

RESET Pulse Width

5

ms

CLOCK OUTPUTS

LLC Mark Space Ratio

t9:t10

45:55

55:45

% duty cycle

DATA AND CONTROL OUTPUTS

Data Output Transitional Time

t11

Negative clock edge to start of valid data

(tACCESS = t10 − t11)

3.8

ns

t12

End of valid data to negative clock edge

(tHOLD = t9 + t12)

6.9

ns

Timing Diagrams

Figure 2. I2C Timing

Figure 3. Pixel Port and Control Output Timing

SDATA

SCLK

t3

t5

t3

t4

t8

t6

t7

t2

t1

OUTPUT LLC

OUTPUTS P0 TO P7, HS,

VS/FIELD/SFL

t9

t10

t11

t12

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