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AD5687RBRUZ Fiches technique(PDF) 7 Page - Analog Devices

No de pièce AD5687RBRUZ
Description  Dual, 16-/12-Bit nanoDAC with 2 ppm/째C Reference, SPI Interface
Download  28 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD5687RBRUZ Fiches technique(HTML) 7 Page - Analog Devices

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Data Sheet
AD5689R/AD5687R
Rev. 0 | Page 7 of 28
DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4
and Figure 5. VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted. VDD =
2.7 V to 5.5 V.
Table 5.
1.8 V
≤ VLOGIC < 2.7 V
2.7 V
≤ VLOGIC ≤ 5.5 V
Parameter1
Min
Max
Min
Max
Unit
Description
t1
66
40
ns
SCLK cycle time
t2
33
20
ns
SCLK high time
t3
33
20
ns
SCLK low time
t4
33
20
ns
SYNC to SCLK falling edge
t5
5
5
ns
Data setup time
t6
5
5
ns
Data hold time
t7
15
10
ns
SCLK falling edge to SYNC rising edge
t8
60
30
ns
Minimum SYNC high time
t9
60
30
ns
Minimum SYNC high time
t10
36
25
ns
SDO data valid from SCLK rising edge
t115
15
10
ns
SCLK falling edge to SYNC rising edge
t125
15
10
ns
SYNC rising edge to SCLK rising edge
1
Maximum SCLK frequency is 25 MHz or 15 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
Circuit and Timing Diagrams
Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications
Figure 4. Daisy-Chain Timing Diagram
200µA
IOL
200µA
IOH
VOH (MIN)
TO OUTPUT
PIN
CL
20pF
t4
t5
t6
t8
SDO
SDIN
SYNC
SCLK
48
24
DB23
DB0
DB23
DB0
DB23
INPUT WORD FOR DAC N
UNDEFINED
INPUT WORD FOR DAC N + 1
INPUT WORD FOR DAC N
DB0
t11
t12
t10


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