Agere Systems Inc.

9

Data Sheet, Rev. 3

June 2001

Four-Cable Transceiver/Arbiter Device

FW804 PHY IEEE 1394A

43

TPB0+

Analog I/O Portn, Port Cable Pair B. TPBn is the port B connection to the twisted-

pair cable. Board traces from each pair of positive and negative differen-

tial signal pins should be kept matched and as short as possible to the

external load resistors and to the cable connector.

50

TPB1+

56

TPB2+

37

TPB3+

42

TPB0

−

Analog I/O Portn, Port Cable Pair B. TPBn is the port B connection to the twisted-

pair cable. Board traces from each pair of positive and negative differen-

tial signal pins should be kept matched and as short as possible to the

external load resistors and to the cable connector.

49

TPB1

−

55

TPB2

−

36

TPB3–

46

TPBIAS0

Analog I/O Portn, Twisted-Pair Bias. TPBIAS provides the 1.86 V nominal bias

voltage needed for proper operation of the twisted-pair cable drivers and

receivers and for sending a valid cable connection signal to the remote

nodes.

53

TPBIAS1

59

TPBIAS2

40

TPBIAS3

6, 29, 30, 68,

69, 79

—

34, 35, 47,

48, 54, 62, 63

—

device.

3, 16, 20, 21,

28, 70, 80

—

ground plane.

41, 60, 61,

64, 65

—

low-impedance ground plane.

76

XI

—

Crystal Oscillator. XI and XO connect to a 24.576 MHz parallel reso-

nant fundamental mode crystal. Although, when a 24.576 MHz clock

source is used, it can be connected to XI with XO left unconnected. The

optimum values for the external shunt capacitors are dependent on the

specifications of the crystal used. It is suggested that two 12 pF shunt

capacitors be used for a crystal with a specified 7 pF loading capaci-

tance. For more details, see Crystal Selection Considerations in Applica-

tion Information section.

77

XO

Table 1. Signal Descriptions (continued)

Pin

Signal*

Type

Name/Description

* Active-low signals are indicated by “/” at the beginning of signal names, within this document.