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FW801 Fiches technique(PDF) 1 Page - Agere Systems

No de pièce FW801
Description  One-Cable Transceiver/Arbiter Device
Download  22 Pages
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Fabricant  AGERE [Agere Systems]
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FW801 Fiches technique(HTML) 1 Page - Agere Systems

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Data Sheet, Rev. 1
June 2001
FW801 PHY IEEE * 1394A
One-Cable Transceiver/Arbiter Device
Distinguishing Features
I Compliant with IEEE P1394a Draft 2.0 Standard
for a High Performance Serial Bus (Supple-
ment)
I Supports extended BIAS_HANDSHAKE time for
enhanced interoperability with camcorders
I While unpowered and connected to the bus, will not
drive TPBIAS on a connected port even if receiving
incoming bias voltage on that port
I Does not require external filter capacitors for PLL
I Does not require a separate 5 V supply for 5 V link
controller interoperability
I Interoperable across 1394 cable with 1394 physical
layers (PHY) using 5 V supplies
I Interoperable with 1394 link-layer controllers using
5 V supplies
I Device powerdown feature to conserve energy in
battery-powered applications
I Interface to link-layer controller supports Annex J
electrical isolation as well as bus-keeper isolation
Features
I Provides one fully compliant cable port at
100 Mbits/s, 200 Mbits/s, and 400 Mbits/s
I Fully supports Open HCI requirements
I Supports arbitrated short bus reset to improve
utilization of the bus
I Supports ack-accelerated arbitration and fly-by
concatenation
I Supports connection debounce
I Supports multispeed packet concatenation
I Supports PHY pinging and remote PHY access
packets
I Fully supports suspend/resume
I Supports PHY-link interface initialization and reset
I Supports 1394a register set
I Supports LPS/link-on as a part of PHY-link inter-
face
I Supports provisions of IEEE 1394-1995 Standard
for a High Performance Serial Bus
I Fully interoperable with FireWire
implementation
of IEEE 1394-1995
I Reports cable power fail interrupt when voltage at
CPS pin falls below 7.5 V
I Separate cable bias and driver termination voltage
supply for port
Other Features
I 48-pin TQFP package
I Single 3.3 V supply operation
I Data interface to link-layer controller provided
through 2/4/8 parallel lines at 50 Mbits/s
I 25 MHz crystal oscillator and PLL provide transmit/
receive data at 100 Mbits/s, 200 Mbits/s, and
400 Mbits/s and link-layer controller clock at
50 MHz
I Multiple separate package signals provided for
analog and digital supplies and grounds
Description
The Agere Systems Inc. FW801 device provides the
analog physical layer functions needed to imple-
ment a one-port node in a cable-based IEEE 1394-
1995 and IEEE P1394a network.
The cable port incorporates two differential line
transceivers. The transceivers include circuitry to
monitor the line conditions as needed for determin-
ing connection status, for initialization and
arbitration, and for packet reception and transmis-
sion. The PHY is designed to interface with a link-
layer controller (LLC).
* IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
† FireWire is a registered trademark of Apple Computer, Inc.


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