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AD8362-EVAL Datasheet(Fiches technique) 20 Page - Analog Devices

Numéro de pièce AD8362-EVAL
Description  50 Hz to 2.7 GHz 60 dB TruPwr™ Detector
Télécharger  36 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
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AD8362
Rev. B | Page 20 of 36
USING THE AD8362
The AD8362 requires a single supply of nominally 5 V; its
performance is essentially unaffected by variations of up to
±10%, the range over which the stated specifications apply.
Supplies as low as 2.7 V may be used with some loss of
performance at high inputs and at temperature extremes.
The AD8362 is disabled by a logic high on the PWDN pin,
which may be directly grounded for continuous operation,
when the supply current at 27°C is nominally 24 mA and
essentially independent of supply voltage. When powered
down by a logic low on PWDN, the supply current is reduced
to about 275 µA.
BASIC CONNECTIONS
The supply is connected to the VPOS pin using the decoupling
network shown in Figure 48, whose capacitors must provide a
low impedance over the full frequency range of the input, and
should be placed as close as possible to the VPOS pin. Two
different capacitors are used in parallel to reduce the overall
impedance since these have different resonant frequencies.
However, the measurement accuracy is not critically dependent
on supply decoupling because the high frequency signal path is
confined to the relevant input pins. It is more important that the
lead lengths to INHI and INLO, and in the decoupling
capacitors from both of the DECL pins to ground, and the
connections from COMM to the ground plane all use the
shortest possible connections.
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
COMM
CHPF
DECL
INHI
INLO
DECL
PWDN
COMM
ACOM
VREF
VTGT
VPOS
VOUT
VSET
ACOM
CLPF
1nF
VOUT
AD8362
SIGNAL INPUT
Z = 2
× 100Ω
1mV – 1V rms
LOGIC HIGH FOR
POWER-DOWN
CDEC
CLPF
VS
+5V nom, @ 24mA
0.1
µF
3.3
CCPL
CDEC
CDEC
Figure 48. Basic Measurement Mode Connections




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