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AD8362EVAL Datasheet(Fiches technique) 16 Page  Analog Devices 

16 page AD8362 Rev. B  Page 16 of 36 Accordingly, VTGT (and its fractional part VATG) determines the output that must be provided by the VGA for the AGC loop to settle. Since the scaling parameters of the two squarers are accurately matched, it follows that Equation 3 is satisfied only when () 2 2 ATG SIG V V MEAN = (4) In a formal solution, one would then extract the square root of both sides to provide an explicit value for the rootmeansquare (rms) value. However, it is apparent that by forcing this identity, through varying the VGA gain and extracting the mean value by the filter provided by the capacitor(s), the system inherently establishes the relationship ( ) ATG SIG V V rms = (5) Substituting the value of VSIG from Equation 2, we have ( ) [ ] ATG GNS IN O V V VSET V G rms = − exp (6) As a measurement device, VIN is the unknown quantity and all other parameters can be fixed by design. Solving Equation 6: [ ] ( ) GNS ATG IN O V VSET V V G rms exp = (7) so () [ ] Z IN GNS V V rms V VSET log = (8) The quantity VZ = VATG/GO is defined as the intercept voltage because VSET must be 0 when rms (VIN) = VZ. When connected as a measurement device, the output of the buffer is tied directly to VSET, which closes the AGC loop. Making the substitution VOUT = VSET and changing the log base to 10, as needed in a decibel conversion, we have () [ ] Z IN SLP V V rms V VOUT 10 log = (9) where VSLP is the slope voltage, that is, the change in output voltage for each decade of change in the input amplitude. (Note that VSLP = VGNS log (10) = 2.303 VGNS). In the AD8362, VSLP is laser trimmed to 1 V using a 100 MHz test signal. Because a decade corresponds to 20 dB, this slope may also be stated as 50 mV/dB. It is later shown how the effective value of VSLP may be altered by the user. Likewise, the intercept VZ is also laser trimmed to 316 µV (−70 dBV). In an ideal system, VOUT would cross zero for an rms input of that value. In a singlesupply realization of the function, VOUT cannot run fully down to ground; here, VZ is the extrapolated value. In measurement modes, the output ranges from 0.5 V for VIN = 1 mV (input values are stated as rms, outputs values as dc), up to a voltage 60 dB × 50 mV/dB = 3 V above this for VIN = 1 V, that is, to 3.5 V. Figure 43 shows the ideal form of Equation 9 scaled as in the AD8362. RMS INPUT VOLTAGE (100 µV TO 3.2V) 0 100 µV 1mV 10mV 100mV 1V 10V 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Figure 43. Ideal Response of the AD8362 EFFECT OF INPUT COUPLING ON THE INTERCEPT VALUE Reductions of VIN due to coupling losses directly affect VZ. In high frequency applications, several factors contribute to the coupling of the source into the IC, including the board and package resonances and attenuation. Any uncertainties in the input impedance result in the intercept expressed in power terms, which is nominally −57 dBm for a 50 Ω system, being less accurately determined than when stated in dBV (that is, in pure voltage) terms. On the other hand, the slope VSLP is unaffected by all such impedance or coupling uncertainties. OFFSET ELIMINATION To address the small dc offsets that arise in the variable gain amplifier, an offsetnulling loop is used. The highpass corner frequency of this loop is internally preset to 1 MHz, sufficiently low for most HF applications. When using the AD8362 in LF applications, the corner frequency can be reduced as needed by the addition of a capacitor from the CHPF pin to ground having a nominal value of 200 µF/Hz. For example, to lower the high pass corner frequency to 150 Hz, a capacitance of 1.33 µF is required. The offset voltage varies depending on the actual gain at which the VGA is operating, and thus, on the input signal amplitude. Baseline variations of this sort are a common aspect of all VGAs, although more evident in the AD8362 because of the method of its implementation, which causes the offsets to ripple along the gain axis with a period of 6.33 dB. When an excessively large value of CHPF is used, the offset correction process may lag the more rapid changes in the VGA’s gain, which may increase the time required for the loop to fully settle for a given steady input amplitude. 
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