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DAC8043AES Fiches technique(PDF) 2 Page - Analog Devices |
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DAC8043AES Fiches technique(HTML) 2 Page - Analog Devices |
2 / 8 page REV. 0 –2– DAC8043A–SPECIFICATIONS Parameter Symbol Condition E Grade F Grade Units STATIC PERFORMANCE Resolution N 12 12 Bits Relative Accuracy INL ±0.5 ±1.0 LSB max Differential Nonlinearity DNL All Grades Monotonic to 12 Bits ±0.5 ±1.0 LSB max Gain Error 1 GFSE TA = +25°C, Data = FFFH ±1.0 ±2.0 LSB max TA = –40°C, +85°C, Data = FFFH ±2.0 ±2.0 LSB max Gain Tempco 2 TCGFS IOUT Pin Measured ±5 ±5 ppm/ °C max Output Leakage Current ILKG Data = 000H, IOUT Pin Measured ±5 ±5 nA max TA = –40°C, +85°C, Data = 000H, IOUT Pin Measured ± 25 ±25 nA max Zero-Scale Error 3 IZSE Data = 000H 0.03 0.03 LSB max TA = –40°C, +85°C, Data = 000H 0.15 0.15 LSB max REFERENCE INPUT Input Resistance RREF Absolute Tempco < 50 ppm/ °C 7/15 7/15 k Ω min/max Input Capacitance 2 CREF 5 5 pF typ ANALOG OUTPUT Output Capacitance 2 COUT Data = 000H 25 25 pF typ Data = FFFH 30 30 pF typ DIGITAL INPUTS Digital Input Low VIL 0.8 0.8 V max Digital Input High VIH 2.4 2.4 V min Input Leakage Current IIL VLOGIC = 0 V to +5 V 0.001/ ± 1 0.001/± 1 µA typ/max Input Capacitance 2 CIL VLOGIC = 0 V 10 10 pF max INTERFACE TIMING 2, 4 Data Setup tDS 10 10 ns min Data Hold tDH 5 5 ns min Clock Width High tCH 25 25 ns min Clock Width Low tCL 25 25 ns min Load Pulsewidth tLD 25 25 ns min LSB CLK to LD DAC tASB 0 0 ns min AC CHARACTERISTICS 1, 2 Output Current Settling Time tS To ±0.01% of Full Scale, Ext Op Amp OP42 1 1 µs max DAC Glitch Q Data = 000H to FFFH to 000H, VREF = 0 V 20 20 nVs max Feedthrough (VOUT/VREF)FT VREF = 20 V p-p, Data = 000H, f = 10 kHz 1 1 mV p-p Total Harmonic Distortion THD VREF = 6 V rms, Data = FFFH, f = 1 kHz –85 –85 dB typ Output Noise Density 5 en 10 Hz to 100 kHz Between RFB and IOUT 17 17 nV/ √Hz max Multiplying Bandwidth BW –3 dB, VOUT/VREF, VREF = 100 mV rms, Data = FFFH 2.4 2.4 MHz typ SUPPLY CHARACTERISTICS Power Supply Range VDD RANGE 4.5/5.5 4.5/5.5 V min/max Positive Supply Current IDD VLOGIC = 0 V or VDD 10 10 µA max Power Dissipation PDISS VLOGIC = 0 V or VDD 50 50 µW max Power Supply Sensitivity PSS ∆V DD = ± 5% 0.002 0.002 %/% max NOTES 1Using internal feedback resistor R FB, see Figure 19 test circuit with V REF = +10 V. 2These parameters are guaranteed by design and not subject to production testing. 3Calculated from worst case R REF: IZSE(LSB) = (RREF × ILKG × 4096)/VREF. 4All input control signals are specified with t R = tF = 2 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 5Calculation from e n = √4KTRB where: K = Boltzmann Constant (J/ °K), R = Resistance (Ω), T = Resistor Temperature (°K), B = 1 Hz Bandwidth. Specifications subject to change without notice. ELECTRICAL CHARACTERISTICS (@ V DD = +5 V, VREF = +10 V, –40 C < TA < +85 C, unless otherwise noted.) |
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