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ADV7152 Fiches technique(PDF) 5 Page - Analog Devices |
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ADV7152 Fiches technique(HTML) 5 Page - Analog Devices |
5 / 32 page ADV7152 –5– REV. B PIXEL INPUT DATA* CLOCK LOADOUT LOADIN ANALOG OUTPUT DATA t 10 AN BN AN+1 BN+1 AN-1 BN-1 AN+2 BN+2 AN BN AN+1BN+1 AN+2BN+2 DIGITAL INPUT TO ANALOG OUTPUT PIPELINE t PD *INCLUDES PIXEL DATA (R0–R7, G0–G7, B0–B7); PALETTE SELECT INPUTS (PS0-PS1); SYNC; BLANK IOR, IOR IOG, IOG IOB, IOB I PLL, SYNCOUT Figure 4. Pixel Input to Analog Output Pipeline with Minimum LOADOUT to LOADIN Delay (2:1 Multiplex Mode) PIXEL INPUT DATA* CLOCK LOADOUT LOADIN ANALOG OUTPUT DATA *INCLUDES PIXEL DATA (R0–R7, G0–G7, B0–B7); PALETTE SELECT INPUTS (PS0–PS1); SYNC; BLANK DIGITAL INPUT TO ANALOG OUTPUT PIPELINE AN BN AN+1BN+1 AN+2BN+2 AN BN AN+1 BN+1 AN-1 BN-1 AN+2 BN+2 t PD τ τ- t 11 IOR, IOR IOG, IOG IOB, IOB I PLL, SYNCOUT Figure 5. Pixel Input to Analog Output Pipeline with Maximum LOADOUT to LOADIN Delay (2:1 Multiplex Mode) t 12 CLOCK PRGCKOUT (CLOCK/4) PRGCKOUT (CLOCK/8) PRGCKOUT (CLOCK/16) PRGCKOUT (CLOCK/32) *INLCUDES PIXEL DATA (R0-R7, G0-G7, B0-B7); PALETTE SELECT INPUTS (PS0-PS1); SYNC; BLANK Figure 6. Pixel Clock Input vs. Programmable Clock Output (PRGCKOUT) |
Numéro de pièce similaire - ADV7152 |
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Description similaire - ADV7152 |
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