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ADMCF341BR Fiches technique(PDF) 7 Page - Analog Devices |
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ADMCF341BR Fiches technique(HTML) 7 Page - Analog Devices |
7 / 36 page REV. 0 ADMCF341 –7– GENERAL DESCRIPTION The ADMCF341 is a low-cost, single-chip DSP-based control- ler, suitable for permanent magnet synchronous motors, ac induction motors, and brushless dc motors. The ADMCF341 integrates a 20 MHz, fixed-point DSP core with a complete set of motor control and system peripherals that permits fast, efficient development of motor controllers. The DSP core of the ADMCF341 is completely code-compatible with the ADSP-21xx DSP family and combines three computa- tional units, data address generators, and a program sequencer. The computational units are an ALU, a multiplier/accumulator (MAC), and a barrel shifter. There are special instructions for bit manipulation, multiplication ( squared), biased rounding, and global interrupt masking. The system peripherals are the power-on reset circuit (POR), the watchdog timer, and two synchronous serial ports. The serial ports are configurable and double buffered, with hardware support for UART, SCI, and SPI port emulation. The ADMCF341 provides 512 24-bit program memory RAM, 4K 24-bit program memory ROM, 4K 24-bit program FLASH memory, and 512 16-bit data memory RAM. The user code can be stored and executed from the flash memory. The program and data memory RAM can be used for dynamic data storage or can be loaded through the serial port from an external device as in other ADMCxxx family parts. The program memory ROM contains a monitor function as well as useful routines for erasing, programming, and verifying the flash memory. The motor control peripherals of the ADMCF341 provide a 12-bit analog data acquisition system with six analog input channels with three dedicated ISENSE inputs (combining internal amplification, sampling, and overcurrent PWM shutdown features) and an internal voltage reference. In addition, a three- phase, 16-bit, center-based PWM generation unit can be used to produce high accuracy PWM signals with minimal processor overhead. The ADMCF341 also contains two 16-bit auxiliary PWM timer outputs and nine lines of digital I/O. Because the ADMCF341 has a limited number of pins, functions such as the auxiliary PWM timers and the serial communication ports are multiplexed with the nine programmable digital input/ output (PIO) pins. The pin functions can be independently selected to allow maximum flexibility for different applications. DSP CORE ARCHITECTURE OVERVIEW Figure 3 is an overall block diagram of the DSP core of the ADMCF341. The flexible architecture and comprehensive instruction set allow the processor to perform multiple opera- tions in parallel. In one processor cycle (50 ns with a 10 MHz CLKIN) the DSP core can: ∑ Generate the next program address ∑ Fetch the next instruction ∑ Perform one or two data moves ∑ Update one or two data address pointers ∑ Perform a computational operation This all takes place while the processor continues to: ∑ Receive and transmit through the serial ports ∑ Decrement the interval timer ∑ Generate three-phase PWM waveforms for a power inverter ∑ Generate two signals using the 16-bit auxiliary PWM timers ∑ Acquire four analog signals ∑ Decrement the watchdog timer PM ROM 4K 24 PM RAM 512 24 BUS EXCHANGE COMPANDING CIRCUITRY DATA ADDRESS GENERATOR #2 DATA ADDRESS GENERATOR #1 14 14 24 16 6 DM RAM 512 16 R BUS 16 DMA BUS PMA BUS DMD BUS PMD BUS INSTRUCTION REGISTER INPUT REGS OUTPUT REGS SHIFTER CONTROL LOGIC SERIAL PORT RECEIVE REG TRANSMIT REG TIMER INPUT REGS OUTPUT REGS MAC INPUT REGS OUTPUT REGS ALU PROGRAM SEQUENCER FLASH PROGRAM MEMORY 4K 24 Figure 3. DSP Core Block Diagram |
Numéro de pièce similaire - ADMCF341BR |
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Description similaire - ADMCF341BR |
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