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AD9561JR Fiches technique(PDF) 2 Page - Analog Devices

No de pièce AD9561JR
Description  Pulse Width Modulator
Download  8 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD9561JR Fiches technique(HTML) 2 Page - Analog Devices

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AD9561–SPECIFICATIONS (+V
S = +5 V; RSET = 715
, CLOCK = 20 MHz unless otherwise noted)
AD9561JR
Parameter
Temp
Min
Typ
Max
Units
RESOLUTION
8
Bits
ACCURACY (@ 20 MHz)
Differential Nonlinearity
+25
°C
±0.5
±2
LSB
Integral Linearity
1
+25
°C
±1.5
±4
LSB
Odd/Even Pulse Mismatch
2
+25
°C
±0.75
LSB
DIGITAL INPUTS
Logic “1” Voltage
Full
2.0
V
Logic “0” Voltage
Full
0.8
V
Input Current
Full
±1
µA
Input Capacitance
+25
°C
5pF
Data Setup Time
Full
2.0
0.3
ns
Data Hold Time
Full
2.0
0.3
ns
Minimum Clock Pulse Width (HIGH)
Full
6
ns
DYNAMIC PERFORMANCE
Maximum Trigger Rate
Full
60
MHz
Minimum Propagation Delay (tPD)
3
+25
°C
122028ns
Minimum Propagation Delay TC
Full
60
ps/
°C
Output Pulse Width @ Code 254
Full
5
ns
Output Pulse Width @ Code 255
Full
100
% Clock
Output Rise Time
5, 6
Full
1.8
3
ns
Output Fall Time5, 6
Full
1.8
3
ns
RETRACE Propagation Delay
Full
6
ns
PWM OUTPUT
Logic “1” Voltage
5, 6
Full
4.6
V
Logic “0” Voltage
5, 6
Full
0.4
V
CAL OUT
Logic “1” Voltage
Full
4.6
V
Logic “0” Voltage
Full
0.4
V
POWER SUPPLY7
Positive Supply Current (+5.0 V)
Full
140
170
mA
Power Dissipation
Full
700
850
mW
Power Reduce Current
Full
70
85
mA
Power Reduce Dissipation
Full
350
425
mW
Power Supply Rejection Ratio
Propagation Delay Sensitivity (TEM)8
+25
°C
1.5
ns/V
NOTES
1Best Fit between codes 25 and 230. INL is very layout sensitive.
2Due to linearity mismatch in dual ramps.
3Measured from rising edge of clock to transition of Codes 0 to 255.
4Minimum pulse width (at 20 MHz) limited by rise time. Pulse width for Code 25 will be greater when CLOCK < 20 MHz.
5Output load = 10 pF and 2 mA source/sink.
6Load conditions to test output drive capability. Linearity will degrade with either capacitive or current loading. Best linearity obtained driving a single CMOS input.
7All performance specifications valid when supply maintained at +5 V,
± 5%.
8Tested from +4.75 V to +5.25 V.
Specification subject to change without notice.


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