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AD9483KS-100 Fiches technique(PDF) 1 Page - Analog Devices |
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AD9483KS-100 Fiches technique(HTML) 1 Page - Analog Devices |
1 / 26 page REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD9483 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 Triple 8-Bit, 140 MSPS A/D Converter FUNCTIONAL BLOCK DIAGRAM 8 T/H QUANTIZER AD9483 TIMING R AIN R AIN G AIN G AIN B AIN B AIN ENCODE ENCODE DS DS VREF OUT RVREF IN GVREF IN BVREF IN VCC VDD GND PD I/P OMS CLKOUT CLKOUT DBB7-0 DBA7-0 DGB7-0 DGA7-0 DRB7-0 DRA7-0 8 T/H QUANTIZER 8 T/H QUANTIZER CONTROL +2.5V FEATURES 140 MSPS Guaranteed Conversion Rate 100 MSPS Low Cost Version Available 330 MHz Analog Bandwidth 1 V p-p Analog Input Range Internal +2.5 V Reference Differential or Single-Ended Clock Input 3.3 V/5.0 V Three-State CMOS Outputs Single or Demultiplexed Output Ports Data Clock Output Provided Low Power: 1.0 W Typical +5 V Converter Power Supply APPLICATIONS RGB Graphics Processing High Resolution Video LCD Monitors and Projectors Micromirror Projectors Plasma Display Panels Scan Converters GENERAL DESCRIPTION The AD9483 is a triple 8-bit monolithic analog-to-digital converter optimized for digitizing RGB graphics signals from personal computers and workstations. Its 140 MSPS encode rate capability and full-power analog bandwidth of 330 MHz supports display resolutions of up to 1280 × 1024 at 75 Hz with sufficient input bandwidth to accurately acquire and digitize each pixel. To minimize system cost and power dissipation, the AD9483 includes an internal +2.5 V reference and track-and-hold cir- cuit. The user provides only a +5 V power supply and an en- code clock. No external reference or driver components are required for many applications. The digital outputs are three- state CMOS outputs. Separate output power supply pins sup- port interfacing with 3.3 V or 5 V logic. The AD9483’s encode input interfaces directly to TTL, CMOS, or positive-ECL logic and will operate with single-ended or differential inputs. The user may select dual channel or single channel digital outputs. The Dual Channel (demultiplexed) mode interleaves ADC data through two 8-bit channels at one- half the clock rate. Operation in Dual Channel mode reduces the speed and cost of external digital interfaces while allowing the ADCs to be clocked to the full 140 MSPS conversion rate. In the Single Channel mode, all data is piped at the full clock rate to the Channel A outputs and the ADCs conversion rate is limited to 100 MSPS. A data clock output is provided at the Channel A output data rate for both Dual-Channel or Single- Channel output modes. Fabricated in an advanced BiCMOS process, the AD9483 is provided in a space-saving 100-lead MQFP surface mount plas- tic package (S-100) and is specified over the 0 °C to +85°C temperature range. |
Numéro de pièce similaire - AD9483KS-100 |
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Description similaire - AD9483KS-100 |
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