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AD818AR-REEL7 Fiches technique(PDF) 11 Page - Analog Devices |
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AD818AR-REEL7 Fiches technique(HTML) 11 Page - Analog Devices |
11 / 12 page AD818 REV. B –11– AD829 100 0.47µF 0.01µF –VS 0.47µF 0.01µF +VS SHORT, DIRECT CONNECTION TO TEKTRONIX TYPE 11402 OSCILLOSCOPE PREAMP INPUT SECTION 15pF 1M SETTLING OUTPUT 2 × HP2835 ERROR AMPLIFIER VERROR OUTPUT × 10 1.9k 100 AD818 0.01µF –VS 0.01µF 2.2µF +VS 2.2µF 10pF SCOPE PROBE CAPACITANCE TEKTRONIX P6201 FET PROBE TO TEKTRONIX TYPE 11402 OSCILLOSCOPE PREAMP INPUT SECTION 500 5–18pF DEVICE UNDER TEST NOTE: USE CIRCUIT BOARD WITH GROUND PLANE FALSE SUMMING NODE NULL ADJUST 1k 100 1k 50 COAX CABLE TTL LEVEL SIGNAL GENERATOR 50Hz OUTPUT 2 13 1, 14 7, 8 DIGITAL GROUND ANALOG GROUND 0 TO ±10V POWER SUPPLY EI&S DL1A05GM MERCURY RELAY ERROR SIGNAL OUTPUT 500 50 2 3 5 6 4 7 2 × HP2835 2 3 6 7 4 Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Figure 37. Settling Time Test Circuit DIFFERENTIAL LINE RECEIVER The differential receiver circuit of Figure 39 is useful for many applications from audio to video. It allows extraction of a low level signal in the presence of common-mode noise. As shown in Figure 40, the AD818 provides this function with only 10 nV/ √Hz noise at the output. VOUT 2pF DIFFERENTIAL INPUT +5V –5V OUTPUT AD818 0.01 F 2.2 F 2 3 6 4 7 0.01 F 2.2 F 2pF 1k 1k 1k 1k Figure 39. Differential Line Receiver 200 V 10n s 200m V 10 90 100 0% 1V 2V 20ns Figure 40. Performance of Line Receiver, RL = 150 Ω, G = +2 AD818 SETTLING TIME Settling time is comprised primarily of two regions. The first is the slew time in which the amplifier is overdriven, where the output voltage rate of change is at its maximum. The second is the linear time period required for the amplifier to settle to within a specified percent of the final value. Measuring the rapid settling time of AD818 (45 ns to 0.1% and 80 ns to 0.01%—10 V step) requires applying an input pulse with a very fast edge and an extremely flat top. With the AD818 configured in a gain of –1, a clamped false summing junction responds when the output error is within the sum of two diode voltages (approximately 1 volt). The signal is then amplified 20 times by a clamped amplifier whose output is connected directly to a sampling oscilloscope. A High Performance Video Line Driver The buffer circuit shown in Figure 38 will drive a back-termi- nated 75 Ω video line to standard video levels (1 V p-p) with 0.1 dB gain flatness to 55 MHz with only 0.05 ° and 0.01% differential phase and gain at the 3.58 MHz NTSC subcarrier frequency. This level of performance, which meets the require- ments for high-definition video displays and test equipment, is achieved using only 7 mA quiescent current. +15V VIN –15V AD818 0.01µF 2.2µF 2 3 6 4 7 0.01µF 2.2µF Rt 75 Ω Rbt 75 Ω 75 Ω Rt 75 Ω 1k Ω 1k Ω Figure 38. Video Line Driver |
Numéro de pièce similaire - AD818AR-REEL7 |
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Description similaire - AD818AR-REEL7 |
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