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AD7884BN Fiches technique(PDF) 3 Page - Analog Devices

No de pièce AD7884BN
Description  LC2MOS 16-Bit, High Speed Sampling ADCs
Download  16 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD7884BN Fiches technique(HTML) 3 Page - Analog Devices

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AD7884/AD7885
REV. C
–3–
TIMING CHARACTERISTICS1, 2
Limit at +25 C
Limit at TMIN, TMAX
Parameter
(All Versions)
(A, B Versions)
Units
Conditions/Comments
t1
50
50
ns min
CONVST
Pulse Width
t2
100
100
ns max
CONVST
to BUSY Low Delay
t3
0
0
ns min
CS
to RD Setup Time
t4
60
60
ns min
RD
Pulse Width
t5
0
0
ns min
CS
to RD Hold Time
t6
2
57
57
ns max
Data Access Time after RD
t7
3
5
5
ns min
Bus Relinquish Time after RD
50
50
ns max
t8
40
40
ns min
New Data Valid before Rising Edge of BUSY
t9
10
80
ns min
HBEN to RD Setup Time
t10
25
25
ns min
HBEN to RD Hold Time
t11
60
60
ns min
HBEN Low Pulse Duration
t12
60
60
ns min
HBEN High Pulse Duration
t13
55
70
ns max
Propagation Delay from HBEN Falling to Data Valid
t14
55
70
ns max
Propagation Delay from HBEN Rising to Data Valid
NOTES
1Timing specifications in bold print are 100% production tested. All other times are sample tested at +5
°C to ensure compliance. All input signals are specified
with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2t
6 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3t
7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrap-
olated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t 7, quoted in the Timing Characteristics is the true
bus relinquish time of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
(VDD = +5 V
5%, VSS = –5 V
5%, AGND = DGND = GND = 0 V. See Figures 2, 3, 4 and 5.)
ORDERING GUIDE
Linearity
Temperature
Error
SNR
Package
Model
1
Range
(% FSR)
(dB)
Option
2
AD7884AN
–40
°C to +85°C
84
N-40A
AD7884BN
–40
°C to +85°C ±0.0075
84
N-40A
AD7884AP
–40
°C to +85°C
84
P-44A
AD7884BP
–40
°C to +85°C ±0.0075
84
P-44A
AD7885AN
–40
°C to +85°C
84
N-28A
AD7885BN
–40
°C to +85°C ±0.0075
84
N-28A
AD7885AAP –40
°C to +85°C
84
P-44A
AD7885ABP –40
°C to +85°C ±0.0075
84
P-44A
NOTES
1Analog Devices reserves the right to ship cerdip (Q) packages in lieu of plastic
DIP (N) packages.
2N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC).
TO OUTPUT PIN
+2.1V
I
OH
I OL
C L
100pF
1.6mA
200
µA
Figure 1. Load Circuit for Access Time and Bus Relinquish
Time


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