AD7821

REV. A

–6–

PIN FUNCTION DESCRIPTION

Pin

Mnemonic Description

≤ V

IN

≤

2

DB0

Three-State Data Output (LSB).

3–5

DB1–DB3

Three-State Data Outputs.

6

WR

/RDY

WRITE control input/READY status

output. See Digital Interface section.

7

MODE

Mode Selection Input. It determines

whether the device operates in the

WR-RD or RD mode. This input is in-

ternally pulled low through a 50

µA

current source. See Digital Interface

section.

8

RD

READ Input. RD must be low to access

data from the part. See Digital Interface

section.

9

INT

INTERRUPT Output. INT going low

indicates that the conversion is complete.

INT

returns high on the rising edge of

CS

or RD. See Digital Interface section.

10

GND

Ground.

11

Lower limit of reference span.

≤ V

≤ V

12

Upper limit of reference span.

≤ V

13

CS

Chip Select Input. The device is selected

when this input is low.

14–16

DB4–DB6

Three-State Data Outputs.

17

DB7

Three-State Data Output (MSB).

18

OFL

Overflow Output. If the analog input is

will be low at the end of conversion. It is

a non-three-state output which can be

used to cascade 2 or more devices to

increase resolution.

19

Negative supply voltage.

20

Positive supply voltage, +5 V.

CIRCUIT INFORMATION

BASIC DESCRIPTION

The AD7821 uses a half flash conversion technique (see Func-

tional Block Diagram), whereby two 4-bit flash ADCs are used

to achieve an 8-bit result. Each 4-bit flash ADC contains 15

comparators, which compare an unknown input voltage to the

reference ladder, to achieve a 4-bit result. The MS (most signifi-

cant) flash ADC converts an unknown analog input voltage

the 4 MS data bits, then recreates an analog approximation of

the input voltage. The DAC output voltage is subtracted from

the analog input, and the difference is converted by the LS

(least significant) ADC to provide the 4 LS data bits. The MS

flash ADC also has one additional comparator to detect over-

range on the analog input.

OPERATING SEQUENCE

The AD7821 has two operating modes. The RD mode allows a

conversion to be started and data to be read with a single, ex-

tended, READ operation (i.e., CS and RD are taken low). The

conversion process is timed out by internal one-shots. The WR-

RD mode uses WR to start a conversion and RD to read the

data and allows the conversion timing to be externally con-

trolled. The operating sequence for the WR-RD mode is shown

in Figure 3.

Figure 3. Operating Sequence (WR-RD Mode)

sampled on the falling edge of WR (falling edge of RD, RD

350 ns is required prior to this falling edge. See Digital Interface

section for more details. When WR is low, the internal MS

(most significant) ADC compares the sampled analog input with

the reference ladder to provide the 4 MS data bits. A minimum

of 250 ns is required for this comparison. On the rising edge of

WR

, the MS data result is latched internally and the LS (least

significant) conversion begins, to yield the 4 LS data bits. INT

goes low typically 380 ns after the rising edge of WR. This indi-

cates the LS conversion is complete and that both the LS and

MS data results are latched into the output buffer. RD going

low then enables the output data. If a faster conversion time is

required, the RD line can be brought low 250 ns after WR goes

high. This latches both the LS and MS data bits and outputs the

conversion result on DB0–DB7.

REFERENCE AND INPUT

fully differential and define the zero and full-scale input range of

the ADC. The transfer characteristic of the part is defined by

the integer value of the following expression:

Data (LSBs )

= 256

V

V









+ 0.5

up to provide both unipolar and bipolar operation. The data

output code for unipolar and bipolar operation is Natural Binary

and Offset Binary, respectively.

The span of the analog input voltage can easily be varied.

5 V the sensitivity of the converter can be increased (i.e., if

allows the input span for unipolar operation to be offset from

rangement facilitates ratiometric operation.

Figures 4 and 5 show some configurations which are possible.

For minimum noise a 47

µF capacitor in parallel with a 0.1 µF

capacitor should be connected between the reference inputs and

GND.