AD7776AR datasheet(3/12 Pages) AD

No de pièce	AD7776AR

Description	LC2MOS, High Speed 1-, 4- & 8-Channel 10-Bit ADCs

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AD7776/AD7777/AD7778

–3–

REV. 0

TIMING SPECIFICATIONS1, 2(V

CC = +5 V

5%; AGND = DGND = 0 V; all specifications TMIN to TMAX unless otherwise noted.)

t

3

t

11

t

10

t

9

t

8

FIRST

CONVERSION

FINISHED

(CR6 = 0)

SECOND

CONVERSION

FINISHED (CR6 = 1)

AD7777/AD7778 ONLY

t

9

BUSY

(CR8 = 0)

INT

(CR8 = 1)

t

10

WR, RD

Figure 3. BUSY/INT Timing

IOL

1.6mA

+2.1V

IOH

200

µA

COUT

100pF

DB n

Figure 4. Load Circuit for Bus Timing Characteristics

t1

CS

t2

t4

t5

RD

DB0–DB9

Figure 1. Read Cycle Timing

t1

CS

t2

t6

WR

DB0–DB9

t3

t7

Figure 2. Write Cycle Timing

Parameter

Label

Limit at TMIN to TMAX Units

Test Conditions/Comments

INTERFACE TIMING

CS Falling Edge to WR or RD Falling Edge

t1

0

ns min

WR or RD Rising Edge to CS Rising Edge

t2

0

ns min

WR Pulse Width

t3

53

ns min

CS or RD Active to Valid Data

3

t4

60

ns max

Timed from Whichever Occurs Last

Bus Relinquish Time after

RD

4

t5

10

ns min

45

ns max

Data Valid to

WR Rising Edge

t6

55

ns min

Data Valid after

WR Rising Edge

t7

10

ns min

WR Rising Edge to BUSY Falling Edge

t8

1.5 tCLKIN

ns min

CR9 = 0

2.5 tCLKIN + 70

ns max

WR Rising Edge to BUSY Rising Edge or

INT Falling Edge

t9

19.5 tCLKIN + 70

ns max

Single Conversion, CR6 = 0

t10

33.5 tCLKIN + 70

ns max

Double Conversion, CR6 = 1

WR or RD Falling Edge to INT Rising Edge

t11

60

ns max

CR9 = 1

NOTES

1See Figures 1 to 3.

2Timing specifications in bold print are 100% production tested. All other times are guaranteed by design, not production tested. All input signals are specified with

tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

3t

4 is measured with the load circuit of Figure 4 and defined as the time required for an output to cross 0.8 V or 2.4 V.

4t

5 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured time is then extrapolated back

to remove the effects of charging or discharging the 100 pF capacitor. This means that the time t 5 quoted above is the true bus relinquish time of the device and, as

such, is independent of the external bus loading capacitance.

Specifications subject to change without notice.

Numéro de pièce similaire - AD7776AR

Fabricant	No de pièce	Fiches technique	Description
Analog Devices	AD7776	550Kb / 12P	LC2MOS, High Speed 1-,4-,and 8-Channel 10-Bit ADCs REV. A
Analog Devices	AD7776	550Kb / 12P	LC MOS High Speed 1. 4 nad 8 Channel 10 Bit ADCs REV. A

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Fabricant	No de pièce	Fiches technique	Description
Analog Devices	AD7776	550Kb / 12P	LC2MOS, High Speed 1-,4-,and 8-Channel 10-Bit ADCs REV. A
	AD7824	270Kb / 16P	LC2MOS High Speed 4- & 8-Channel 8-Bit ADCs REV. F
	AD7828KPZ	276Kb / 16P	LC2MOS High Speed 4- and 8-Channel 8-Bit ADCs REV. F
	AD7824KR-REEL	276Kb / 16P	LC2MOS High Speed 4- and 8-Channel 8-Bit ADCs REV. F
	AD7824KNZ	215Kb / 16P	LC2MOS High Speed 4- and 8-Channel 8-Bit ADCs REV. F
	AD7828KNZ	276Kb / 16P	LC2MOS High Speed 4- and 8-Channel 8-Bit ADCs REV. F
	AD7778	550Kb / 12P	LC MOS High Speed 1. 4 and 8 Channel 10 Bit ADCs REV. A
	AD7776	550Kb / 12P	LC MOS High Speed 1. 4 nad 8 Channel 10 Bit ADCs REV. A
	AD7777	550Kb / 12P	LC MOS High Speed 1. 4 and 8 Channel 10 Bit ADCs REV. A
	AD7884	319Kb / 16P	LC2MOS 16-Bit, High Speed Sampling ADCs REV. C

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