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AD7628TQ Fiches technique(PDF) 4 Page - Analog Devices |
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AD7628TQ Fiches technique(HTML) 4 Page - Analog Devices |
4 / 8 page AD7628 –4– REV. A INTERFACE LOGIC INFORMATION DAC Selection Both DAC latches share a common 8-bit input port. The con- trol input DAC A/DAC B selects which DAC can accept data from the input port. Mode Selection Inputs CS and WR control the operating mode of the selected DAC. See Mode Selection Table below. Write Mode When CS and WR are both low, the selected DAC is in the write mode. The input data latches of the selected DAC are transpar- ent and its analog output responds to activity on DB0–DB7. Hold Mode The selected DAC latch retains the data that was present on DB0–DB7 just prior to CS or WR assuming a high state. Both analog outputs remain at the values corresponding to the data in their respective latches. Mode Selection Table DAC A/ DAC B CS WR DAC A DAC B L L L WRITE HOLD H L L HOLD WRITE X H X HOLD HOLD X X H HOLD HOLD L = Low State, H = High State, X = Don’t Care WRITE CYCLE TIMING DIAGRAM CIRCUIT INFORMATION—D/A SECTION The AD7628 contains two identical 8-bit multiplying D/A con- verters, DAC A and DAC B. Each DAC consists of a highly stable thin film R-2R ladder and eight N-channel current steering switches. A simplified D/A circuit for DAC A is shown in Figure 1. An inverted R-2R ladder structure is used; that is, binary Figure 1. Simplified Functional Circuit for DAC A weighted currents are switched between the DAC output and AGND, thus maintaining fixed currents in each ladder leg inde- pendent of switch state. EQUIVALENT CIRCUIT ANALYSIS Figure 2 shows an approximate equivalent circuit for one of the AD7628’s D/A converters, in this case DAC A. A similar equivalent circuit can be drawn for DAC B. Note that AGND (Pin 1) is common for both DAC A and DAC B. The current source ILEAKAGE is composed of surface and junc- tion leakages and, as with most semiconductor devices, approxi- mately doubles every 10 °C. The resistor Ro, as shown in Fig- ure 2, is the equivalent output resistance of the device, which varies with input code (excluding all 0s code) from 0.8R to 2R. R is typically 11 k Ω. C OUT is the capacitance due to the N-channel switches and varies from about 50 pF to 120 pF, depending on the digital input. g(VREF A, N) is the Thevenin equivalent volt- age generator due to the reference input voltage VREF A and the transfer function of the R-2R ladder. For further information on CMOS multiplying D/A converters, refer to “CMOS DAC Application Guide, 2ND Edition” avail- able from Analog Devices, Publication Number G872a–15–4/86. Figure 2. Equivalent Analog Output Circuit of DAC A CIRCUIT INFORMATION–DIGITAL SECTION The input buffers are simple CMOS level-shifters designed so that when the AD7628 is operated with VDD from 10.8 V to 15.75 V, the buffer converts TTL input levels (2.4 V and 0.8 V) into CMOS logic levels. When VIN is in the region of 1.0 volt to 2.0 volts, the input buffers operate in their linear region and pass a quiescent current (see Figure 3). To minimize power sup- ply currents, it is recommended that the digital input voltages be as close to the supply rails (VDD and DGND) as practicably possible. The AD7628 may be operated with any supply voltage in the range 10.8 ≤ V DD ≤ 15.75 volts. Figure 3. Typical Plot of Supply Current, IDD vs. Logic Input Voltage VIN to VDD = +15 V |
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