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AD671SD-500 Fiches technique(PDF) 7 Page - Analog Devices |
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AD671SD-500 Fiches technique(HTML) 7 Page - Analog Devices |
7 / 16 page AD671 REV. B –7– DEFINITIONS OF SPECIFICATIONS INTEGRAL NONLINEARITY (INL) Integral nonlinearity refers to the deviation of each individual code from a line drawn from “zero” through “full scale.” The point used as “zero” occurs 1/2 LSB (1.22 mV for a 10 V span) before the first code transition (all zeros to only the LSB on). “Full scale” is defined as a level 1 1/2 LSB beyond the last code transition (to all ones). The deviation is measured from the low side transition of each particular code to the true straight line. DIFFERENTIAL NONLINEARITY (DNL, NO MISSING CODES) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. Guaranteed no missing codes to 10-bit resolution indicates that all 1024 codes represented by Bits 1–10 must be present over all operating ranges. Guaranteed no missing codes to 11- or 12-bit resolution indicates that all 2048 and 4096 codes, respectively, must be present over all op- erating ranges. UNIPOLAR OFFSET The first transition should occur at a level 1/2 LSB above analog common. Unipolar offset is defined as the deviation of the ac- tual from that point. This offset can be adjusted as discussed later. The unipolar offset temperature coefficient specifies the maximum change of the transition point over temperature, with or without external adjustments. BIPOLAR ZERO In the bipolar mode the major carry transition (0111 1111 1111 to 1000 0000 0000) should occur for an analog value 1/2 LSB below analog common. The bipolar offset error and temperature coefficient specify the initial deviation and maximum change in the error over temperature. GAIN ERROR The last transition (from 1111 1111 1110 to 1111 1111 1111) should occur for an analog value 1 1/2 LSB below the nominal full scale (9.9963 volts for 10.000 volts full scale). The gain er- ror is the deviation of the actual level at the last transition from the ideal level. The gain error can be adjusted to zero as shown in Figures 7, 8 and 9. TEMPERATURE COEFFICIENTS The temperature coefficients for unipolar offset, bipolar zero and gain error specify the maximum change from the initial (+25 °C) value to the value at T MIN or TMAX. POWER SUPPLY REJECTION The only effect of power supply error on the performance of the device will be a small change in gain. The specifications show the maximum full-scale change from the initial value with the supplies at the various limits. SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components, including har- monics but excluding dc. The value for S/N+D is expressed in decibels. EFFECTIVE NUMBER OF BITS (ENOB) ENOB is calculated from the expression SNR = 6.02N + 1.8 dB, where N is equal to the effective number of bits. TOTAL HARMONIC DISTORTION (THD) THD is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured input signal and is ex- pressed as a percentage or in decibels. PEAK SPURIOUS OR PEAK HARMONIC COMPONENT The peak spurious or peak harmonic component is the largest spectral component excluding the input signal and dc. This value is expressed in decibels relative to the rms value of a full- scale input signal. Theory of Operation The AD671 uses a successive subranging architecture. The ana- log to digital conversion takes place in four independent steps or flashes. The analog input signal is subranged to an intermediate residue voltage for the final 12-bit result by utilizing multiple flashes with subtraction DACs (see the AD671 functional block diagram). The AD671 can be configured to operate with unipolar (0 V to +5 V, 0 V to +10 V) or bipolar ( ±5 V) inputs by connecting AIN (Pin 20), REFIN (Pin 19) and BPO/UPO (Pin 21) as shown in Figure 2. The AD671 conversion cycle begins by simply providing an ac- tive HIGH pulse on the ENCODE pin (Pin 16). The rising edge of the ENCODE pulse starts the conversion. The falling edge of the ENCODE pulse is specified to operate within a win- dow of time: less than 30 ns after the rising edge of ENCODE (AD671-500) and less than 50 ns after the falling edge of ENCODE (AD671–750) or after the falling edge of DAV. The time window prevents digitally coupled noise from being intro- duced during the final stages of conversion. An internal timing generator circuit accurately controls all internal timing. AIN BPO/UPO REF IN 20 21 19 AIN ACOM BPO/UPO REF IN 20 22 21 19 AIN BPO/UPO REF IN 20 21 19 AIN AIN AIN 0 TO 10V + 5V REF + 0 TO 5V + 5V REF + 5V TO 5V –+ 5V REF + Figure 2. Input Range Connections |
Numéro de pièce similaire - AD671SD-500 |
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Description similaire - AD671SD-500 |
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