AD532 datasheet(3/7 Pages) AD

No de pièce	AD532

Description	Internally Trimmed Integrated Circuit Multiplier

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Fabricant	AD [Analog Devices]

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–3–

REV. B

AD532

ORDERING GUIDE

Temperature

Package

Model

Ranges

Descriptions

Options

AD532JD

0

°C to +70°C

Side Brazed DIP

D-14

AD532JD/+

0

°C to +70°C

Side Brazed DIP

D-14

AD532KD

0

°C to +70°C

Side Brazed DIP

D-14

AD532KD/+

0

°C to +70°C

Side Brazed DIP

D-14

AD532JH

0

°C to +70°C

Header

H-10A

AD532KH

0

°C to +70°C

Header

H-10A

AD532J Chip

0

°C to +70°C

Chip

AD532SD

–55

°C to +125°C

Side Brazed DIP

D-14

AD532SD/883B

–55

°C to +125°C

Side Brazed DIP

D-14

JM38510/13903BCA –55

°C to +125°C

Side Brazed DIP

D-14

AD532SE/883B

–55

°C to +125°C

LCC

E-20A

AD532SH

–55

°C to +125°C

Header

H-10A

AD532SH/883B

–55

°C to +125°C

Header

H-10A

JM38510/13903BIA

–55

°C to +125°C

Header

H-10A

AD532S Chip

–55

°C to +125°C

Chip

CHIP DIMENSIONS AND BONDING DIAGRAM

Contact factory for latest dimensions.

Dimensions shown in inches and (mm).

Figure 1. Functional Block Diagram

FUNCTIONAL DESCRIPTION

The functional block diagram for the AD532 is shown in Figure

1, and the complete schematic in Figure 2. In the multiplying

and squaring modes, Z is connected to the output to close the

feedback around the output op amp. (In the divide mode, it is

used as an input terminal.)

The X and Y inputs are fed to high impedance differential am-

plifiers featuring low distortion and good common-mode rejec-

tion. The amplifier voltage offsets are actively laser trimmed

to zero during production. The product of the two inputs is

resolved in the multiplier cell using Gilbert’s linearized trans-

conductance technique. The cell is laser trimmed to obtain

VOUT = (X1 – X2)(Y1 – Y2)/10 volts. The built-in op amp is used

to obtain low output impedance and make possible self-contained

operation. The residual output voltage offset can be zeroed at

VOS in critical applications . . . otherwise the VOS pin should be

grounded.

Figure 2. Schematic Diagram

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