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AD1845JP-REEL Fiches technique(PDF) 4 Page - Analog Devices

No de pièce AD1845JP-REEL
Description  Parallel-Port 16-Bit SoundPort Stereo Codec
Download  40 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD1845JP-REEL Fiches technique(HTML) 4 Page - Analog Devices

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AD1845
–4–
REV. C
SYSTEM SPECIFICATIONS
Min
Typ
Max
Units
System Frequency Response Ripple (Line In to Line Out)*
1.0
dB
Differential Nonlinearity*
±1
LSB
Phase Linearity Deviation*
5
Degrees
STATIC DIGITAL SPECIFICATIONS
Min
Max
Units
High Level Input Voltage (VIH)
Digital Inputs
2.4
V
XTAL1I
2.4
V
Low Level Input Voltage (VIL)
0.8
V
High Level Output Voltage (VOH) IOH = –2 mA
2.4
V
Low Level Output Voltage (VOL) IOL = 2 mA
0.4
V
Input Leakage Current
–10
10
µA
Output Leakage Current
–10
10
µA
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE, V DD = VCC = 5.0 V)
Min
Max
Units
WR/RD Strobe Width
(tSTW)
100
ns
WR/RD Rising to WR/RD Falling
(tBWND)80
ns
Write Data Setup to
WR Rising
(tWDSU)10
ns
RD Falling to Valid Read Data
(tRDDV)40
ns
CS Setup to WR/RD Falling
(tCSSU)10
ns
CS Hold from WR/RD Rising
(tCSHD)0
ns
Adr Setup to
WR/RD Falling
(tADSU)10
ns
Adr Hold from
WR/RD Rising
(tADHD)10
ns
DAK Rising to WR/RD Falling
(tSUDK1)20
ns
DAK Falling to WR/RD Rising
(tSUDK2)0
ns
DAK Setup to WR/RD Falling
(tDKSU)10
ns
Data Hold from
RD Rising
(tDHD1)20
ns
Data Hold from
WR Rising
(tDHD2)15
ns
DRQ Hold from
WR/RD Falling
(tDRHD)25
ns
DAK Hold from WR Rising
(tDKHDa)10
ns
DAK Hold from RD Rising
(tDKHDb)
10
ns
DBEN
/DBDIR Delay from WR/RD Falling
(tDBDL)
30
ns
PWRDWN and RESET Low Pulsewidth
300
ns
*Guaranteed, not tested.


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