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SN74ACT72241L15RJ Fiches technique(PDF) 8 Page - Texas Instruments |
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SN74ACT72241L15RJ Fiches technique(HTML) 8 Page - Texas Instruments |
8 / 21 page SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L 512 × 9, 1024 × 9, 2048 × 9, AND 4096 × 9 SYNCHRONOUS FIRST IN, FIRST OUT MEMORIES SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 WCLK tw(CLKH) WEN1 No Operation tc tw(CLKL) Data Valid D0 − D8 tsu(D) th(D) tsu(EN) th(EN) WEN2 (if applicable) No Operation FF RCLK tpd(W-FF) tpd(W-FF) tsk1 (see Note A) REN1, REN2 NOTE A: tsk1 is the minimum time between a rising RCLK edge and a subsequent rising WCLK edge for FF to change logic levels during the current clock cycle. If the time between the rising edge of RCLK and the subsequent rising edge of WCLK is less than tsk1, then FF may not change its logic level until the next WCLK rising edge. Figure 3. Write-Cycle Timing |
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