SN74BCT29846

8BIT BUSINTERFACE DTYPE LATCH

WITH 3STATE OUTPUTS

SCBS023C − MARCH 1989 − REVISED APRIL 1994

Copyright

1

POST OFFICE BOX 655303

POST OFFICE BOX 1443

TTL Outputs Substantially Reduces

Standby Current

and AMD Am29846

Wider Address / Data Paths or Buses With

Parity

DC Loading Effects

DIP (NT)

description

The SN74BCT29846 features 3-state outputs designed specifically for driving highly capacitive or relatively

low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus

drivers, and working registers.

The eight latches of the SN74BCT29846 are transparent D-type latches. The SN74BCT29846 has inverting

data (D) inputs. Since clear (CLR) and preset (PRE) are independent of the clock, taking the CLR input low will

cause the eight Q outputs to go low. Taking the PRE input low will cause the eight Q outputs to go high. When

both PRE and CLR are taken low, the outputs will follow the preset condition.

The buffered output-enable (OE1, OE2, and OE3) inputs can be used to place the eight outputs in either a

normal logic state (high or low levels) or a high-impedance state. The outputs are also in the high-impedance

state during power-up and power-down conditions. The outputs remain in the high-impedance state while the

device is powered-down. In the high-impedance state, the outputs neither load nor drive the bus lines

significantly. The high-impedance state and increased drive provide the capability to drive the bus lines in a

bus-organized system without need for interface or pull-up components. The output enables do not affect the

internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in

the high-impedance state.

The SN74BCT29846 is characterized for operation from 0

°C to 70°C.

FUNCTION TABLE

INPUTS

OUTPUT

PRE

CLR

OE1

OE2

OE3

LE

D

OUTPUT

Q

L

X

L

L

L

X

X

H

H

LL

LL

X

X

L

H

HL

L

L

HL

H

H

HL

L

L

H

H

L

H

HL

L

L

L

X

Q0

X

XX

X

H

XX

Z

X

XX

H

X

XX

Z

X

X

H

X

X

X

X

Z

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

OE1

OE2

1D

2D

3D

4D

5D

6D

7D

8D

CLR

GND

OE3

1Q

2Q

3Q

4Q

5Q

6Q

7Q

8Q

PRE

LE

NT PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.