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74LVC2G17GV-Q100 Fiches technique(PDF) 7 Page - NXP Semiconductors |
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74LVC2G17GV-Q100 Fiches technique(HTML) 7 Page - NXP Semiconductors |
7 / 16 page 74LVC2G17_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 1 — 7 August 2012 7 of 16 NXP Semiconductors 74LVC2G17-Q100 Dual non-inverting Schmitt trigger with 5 V tolerant input 13. Waveforms Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig 5. The input (nA) to output (nY) propagation delays and the output transition times mnb072 nA input nY output tPLH tPHL GND VI VM VM VM VM VOH VOL Table 9. Measurement points Supply voltage Input Output VCC VM VM 1.65 V to 1.95 V 0.5 V CC 0.5 V CC 2.3 V to 2.7 V 0.5 V CC 0.5 V CC 2.7V 1.5V 1.5V 3.0Vto 3.6V 1.5V 1.5V 4.5 V to 5.5 V 0.5 V CC 0.5 V CC Measurement points are given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 6. Test circuit for measuring switching times VEXT VCC VI VO mna616 DUT CL RT RL RL G |
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