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74HCT259BQ-Q100 Fiches technique(PDF) 11 Page - NXP Semiconductors |
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74HCT259BQ-Q100 Fiches technique(HTML) 11 Page - NXP Semiconductors |
11 / 20 page 74HC_HCT259_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 1 — 30 July 2012 11 of 20 NXP Semiconductors 74HC259-Q100; 74HCT259-Q100 8-bit addressable latch Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Address input to output propagation delays 001aah122 An input Qn output tPHL tPLH GND VCC VM VM VOH VOL Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Enable input to output propagation delays and pulse width tPHL VCC GND D input LE input Qn output tTHL tTLH tW VM VY VM VX tPLH VCC GND VOH VOL 001aaj446 Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 9. Master reset input to output propagation delays 001aah124 MR input Qn output tPHL tW VM VOH VCC GND VOL VM |
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