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TPS3813K33MDBVREP Fiches technique(PDF) 1 Page - Texas Instruments

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No de pièce TPS3813K33MDBVREP
Description  PROCESSOR SUPERVISORY CIRCUITS WITH WINDOW-WATCHDOG
Download  16 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

TPS3813K33MDBVREP Fiches technique(HTML) 1 Page - Texas Instruments

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FEATURES
APPLICATIONS
3
2
4
6
(TOP VIEW)
1
WDI
GND
WDT
RESET
VDD
TPS3813
DBV PACKAGE
WDR
5
ACTUAL SIZE
3,00 mm x 3,00 mm
DESCRIPTION
TPS3813J25-EP
,, TPS3813L30-EP
TPS3813K33-EP, TPS3813I50-EP
SGLS343A – MAY 2006 – REVISED MAY 2006
PROCESSOR SUPERVISORY CIRCUITS WITH WINDOW-WATCHDOG
Applications Using DSPs, Microcontrollers,
Controlled Baseline
or Microprocessors
– One Assembly/Test Site, One Fabrication
Safety Critical Systems
Site
Automotive Systems
Extended Temperature Performance of -55
°C
Healing Systems
to 125
°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree (1)
Window-Watchdog With Programmable Delay
and Window Ratio
6-Pin SOT-23 Package
Supply Current of 9
µA (Typ)
Power On Reset Generator With a Fixed
Delay Time of 25 ms
Precision Supply Voltage Monitor 2.5 V, 3 V,
3.3 V, 5 V
Open-Drain Reset Output
(1)
Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
The TPS3813 family of supervisory circuits provides circuit initialization and timing supervision, primarily for
DSPs and processor-based systems.
During power on, RESET is asserted when supply voltage (VDD) becomes higher than 1.1 V. Thereafter, the
supervisory circuit monitors VDD and keeps RESET active as long as VDD remains below the threshold voltage
(VIT). An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset.
The delay time, td = 25 ms typical, starts after VDD has risen above the threshold voltage (VIT). When the supply
voltage drops below the threshold voltage (VIT), the output becomes active (low) again. No external components
are required. All the devices of this family have a fixed-sense threshold voltage (VIT) set by an internal voltage
divider.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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