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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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TMP34094 Fiches technique(PDF) 8 Page - Texas Instruments |
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TMP34094 Fiches technique(HTML) 8 Page - Texas Instruments |
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8 / 38 page  15 40 31 TMS34094 ISA BUS INTERFACE SPVS006A – FEBRUARY 1992 – REVISED JUNE 1992 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 8 data transceiver, with the odd byte overwriting the even byte. If a 16-bit peripheral is sharing the memory segment under investigation, it will issue M16 and allow the TMS34094 to receive the transmission without having to respond with M16. T16 is cleared after reset. SRE, when set to 1, enables direct VGA palette reads of the local palette if SDD is set to 0. This feature is typically used when a VGA controller shares the same physical palette as the TMS34020. SRE is cleared after reset, preventing the local palette from responding to VGA palette reads. PSL selects which half of the LAD bus is connected to a 16-bit memory device when the TMS34020’s dynamic bus sizing feature is used. The TMS34094 uses this bit to determine how to swap data during accesses to the 16-bit device. When the 16-bit device is connected to LAD31–LAD16, PSL should be set to zero. When 16-bit device is connected to LAD15–LAD0, PSL should be set to one. When performing a host access to a device on the LAD bus which does not assert SIZE16, the TMS34094 ignores PSL. PSL is set to zero at reset. IOE enables the I/O mapped interface to the TMS34020 when set to 1. It should be noted that I/O mapped and memory mapped interfaces to the TMS34020 local memory are mutually exclusive. IOE is set to 0 after reset, which enables the memory mapped interface. HI is a transparent read-through of the TMS34020 HINT output. As it is possible for HINT to be activated by a retry or fault on a host access, or by the host/EMU handshake protocol, HINT may be active when the INTOUT bit in HSTCTLL (and therefore in SHDHCTL) is inactive. AI determines how the TMS34094 will increment HADDRH and HADDRL to follow the TMS34020s host address autoincrement mechanism. AI should be set to match the TMS34020s HPFW bit when autoincrement accesses are being performed. The AI bit is set to 0 at reset. 16M3–16M0 are individual M16 enables for each base register. When an access occurs to a memory segment defined by a base register, BASEn, M16 is asserted only if the corresponding bit, 16Mn, is set to 1 and the corresponding BEn bit is set to 1. 16M3–16M0 are cleared after reset, configuring memory maps as 8-bit peripherals. SDD, when set to 1, disables direct VGA palette writes and reads of the local palette. SDD is set to 0 at reset which allows the local palette to respond to VGA palette writes. RS, when set to 1 causes a reset of the TMS34094 and assertion of the RESET signal for at least 4 LCLK1 cycles. RS resets itself to 0. BE3–BE0 are individual enable bits for the base registers. Setting BEn to 1 enables the decode functions of BASEn. The enables are superceded by IOE. When IOE is set to 1, the memory map functions are disabled regardless of BE3–BE0. At reset, BE2–BE0 are set to 0 and BE3 is set to reflect the BIOSEN pin. MAP0E Extended Map Address RESERVED XD Extended Map Address is utilized in extended mapping mode to form a 32-bit register in conjunction with MAP0. It thus provides a 28-bit address completely specifying a 16-bit word in TMS34020 local memory. The extended address is then used as the initial address for a block of data transfers using the autoincrement mode of the TMS34020. The extended map address is uninitialized after reset. XD disables the extended mapping mode when set to 1. The value of XD after reset is 1, thus map extension is disabled by default. Bits 3-1 of MAP0E are reserved and should be set to 0 when MAP0E is written. |
Numéro de pièce similaire - TMP34094 |
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Description similaire - TMP34094 |
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