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TLV320AIC3104 Fiches technique(PDF) 31 Page - Texas Instruments |
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TLV320AIC3104 Fiches technique(HTML) 31 Page - Texas Instruments |
31 / 91 page W0002-01 Decay Time Target Level Input Signal Output Signal AGC Gain Attack Time TLV320AIC3104 www.ti.com SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010 Figure 25. Typical Operation of the AGC Algorithm During Speech Recording Note that the time constants here are correct when the ADC is not in double-rate audio mode. The time constants are achieved using the fS(ref) value programmed in the control registers. However, if the fS(ref) is set in the registers to, for example, 48 kHz, but the actual audio clock or PLL programming actually results in a different fS(ref) in practice, then the time constants would not be correct. The actual AGC decay time maximum is based on a counter length, so the maximum decay time scales with the clock setup that is used. Table 4 shows the relationship of the NCODEC ratio to the maximum time available for the AGC decay. In practice, these maximum times are extremely long for audio applications and should not limit any practical AGC decay time that is needed by the system. STEREO AUDIO DAC The TLV320AIC3104 includes a stereo audio DAC supporting sampling rates from 8 kHz to 96 kHz. Each channel of the stereo audio DAC consists of a digital audio processing block, a digital interpolation filter, multi-bit digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide enhanced performance at low sampling rates through increased oversampling and image filtering, thereby keeping quantization noise generated within the delta-sigma modulator and signal images strongly suppressed within the audio band to beyond 20 kHz. This is realized by keeping the upsampled rate constant at 128 fS(ref) and changing the oversampling ratio as the input sample rate is changed. For an fS(ref) of 48 kHz, the digital delta-sigma modulator always operates at a rate of 6.144 MHz. This ensures that quantization noise generated within the delta-sigma modulator stays low within the frequency band below 20 kHz at all sample rates. Similarly, for an fS(ref) rate of 44.1 kHz, the digital delta-sigma modulator always operates at a rate of 5.6448 MHz. The following restrictions apply in the case when the PLL is powered down and double-rate audio mode is enabled in the DAC. Allowed Q values = 4, 8, 9, 12, 16 Q values where equivalent fS(ref) can be achieved by turning on PLL Q = 5, 6, 7 (set P = 5 / 6 / 7 and K = 16 and PLL enabled) Q = 10, 14 (set P = 5, 7 and K = 8 and PLL enabled) Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback 31 Product Folder Link(s): TLV320AIC3104 |
Numéro de pièce similaire - TLV320AIC3104_12 |
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Description similaire - TLV320AIC3104_12 |
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