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74GTLPH1616DGGRG4 Fiches technique(PDF) 4 Page - Texas Instruments |
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74GTLPH1616DGGRG4 Fiches technique(HTML) 4 Page - Texas Instruments |
4 / 18 page www.ti.com SN74GTLPH1616 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES346C – JANUARY 2001 – REVISED DECEMBER 2005 FUNCTION TABLES abc OUTPUT ENABLE(1) INPUTS OUTPUT MODE B CEAB OEAB LEAB CLKAB A X H X X X Z Isolation L L L H X B0(2) Latched storage of A data L L L L X B0(3) X L H X L L True transparent X L H X H H L L L ↑ L L Clocked storage of A data L L L ↑ H H H L L X X B0(3) Clock inhibit (1) A-to-B data flow is shown; B-to-A data flow is similar, but uses CEBA, OEBA, LEBA, and CLKBA. The condition when OEAB and OEBA are both low at the same time is not recommended. (2) Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low (3) Output level before the indicated steady-state input conditions were established BUFFERED CLOCK INPUTS OPERATION OR MODE FUNCTION CE LE OEAB OEBA X X H H Z Isolation X X L H CLKAB to CLKOUT True delayed clock signal X X H L CLKOUT to CLKIN CLKAB to CLKOUT, True delayed clock signal X X L L CLKOUT to CLKIN with feedback path(1) (1) This condition is not recommended. B-PORT EDGE-RATE CONTROL (ERC) INPUT ERC OUTPUT LOGIC NOMINAL B-PORT EDGE RATE LEVEL VOLTAGE L GND Slow H VCC Fast 4 |
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Description similaire - 74GTLPH1616DGGRG4 |
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