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CDCLVC1112PW Fiches technique(PDF) 4 Page - Texas Instruments

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No de pièce CDCLVC1112PW
Description  3.3 V and 2.5 V LVCMOS High-Performance Clock Buffer Family
Download  23 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

CDCLVC1112PW Fiches technique(HTML) 4 Page - Texas Instruments

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CDCLVC11xx
SCAS895 – MAY 2010
www.ti.com
DEVICE CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
CONDITION
MIN TYP(1)
MAX
UNIT
OVERALL PARAMETERS FOR ALL VERSIONS
1G = VDD; CLKIN = 0 V or VDD; IO = 0 mA; VDD = 3.6 V
6
10
mA
IDD
Static device current(2)
1G = VDD; CLKIN = 0 V or VDD; IO = 0 mA; VDD = 2.7 V
3
6
mA
IPD
Power down current
1G = 0 V; CLKIN = 0 V or VDD; IO = 0 mA; VDD = 3.6 V or 2.7 V
60
µA
VDD = 3.3 V; f = 10 MHz
6
pF
Power dissipation capacitance
CPD
per output(3)
VDD = 2.5 V; f = 10 MHz
4.5
pF
Input leakage current at 1G
± 8
II
VI = 0 V or VDD, VDD = 3.6 V or 2.7 V
µA
Input leakage current at CLKIN
± 25
VDD = 3.3 V
45
Ω
ROUT Output impedance
VDD = 2.5 V
60
Ω
VDD = 3.0 V to 3.6 V
DC
250
MHz
fOUT
Output frequency
VDD = 2.3 V to 2.7 V
DC
180
MHz
OUTPUT PARAMETERS FOR VDD = 3.3 V ± 0.3 V
VDD = 3 V, IOH = –0.1 mA
2.9
VOH
High-level output voltage
VDD = 3 V, IOH = –8 mA
2.5
V
VDD = 3 V, IOH = –12 mA
2.2
VDD = 3 V, IOL = 0.1 mA
0.1
VOL
Low-level output voltage
VDD = 3 V, IOL = 8 mA
0.5
V
VDD = 3 V, IOL = 12 mA
0.8
tPLH,
Propagation delay
CLKIN to Yn
0.8
2.0
ns
tPHL
tsk(o)
Output skew
Equal load of each output
50
ps
tr/tf
Rise and fall time
20%–80% (VOH - VOL)
0.3
0.8
ns
tDIS
Output disable time
1G to Yn
6
ns
tEN
Output enable time
1G to Yn
6
ns
Pulse skew ;
tsk(p)
To be measured with input duty cycle of 50%
180
ps
tPLH(Yn) – tPHL(Yn)
(4)
tsk(pp) Part-to-part skew
Under equal operating conditions for two parts
0.5
ns
tjitter
Additive jitter rms
12kHz…20 MHz, fOUT = 250 MHz
100
fs
(1)
All typical values are at respective nominal VDD. For switching characteristics, outputs are terminated to 50 Ω to VDD/2 (see Figure 1).
(2)
For dynamic IDD over frequency see Figure 8 and Figure 9.
(3)
This is the formula for the power dissipation calculation (see Figure 8 and the Power Consideration section).
Ptot = Pstat + Pdyn + PCload [W]
Pstat = VDD × IDD [W]
Pdyn = CPD × VDD2 × ƒ [W]
PCload = Cload × VDD2 × ƒ × n [W]
n = Number of switching output pins
(4)
tsk(p) depends on output rise- and fall-time (tr/tf). The output duty-cycle can be calculated: odc = (tw(OUT) ± tsk(p))/tperiod; tw(OUT) is
pulse-width of output waveform and tperiod is 1/fOUT.
4
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Product Folder Link(s): CDCLVC11xx


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