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TS2PCIE412RUAR Fiches technique(PDF) 8 Page - Texas Instruments |
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TS2PCIE412RUAR Fiches technique(HTML) 8 Page - Texas Instruments |
8 / 17 page CL (see Note A) TEST CIRCUIT S1 2 × VDD Open GND RL RL 50 Ω VG1 VDD VSEL DUT 50 Ω 50 Ω VG2 50 Ω VI TEST RL S1 V∆ CL VDD VI tPLZ/tPZL 1.5 V to 2 V 2 × VDD 200 Ω GND 10 pF 0.15 V Input Generator Input Generator VO tPHZ/tPZH 1.5 V to 2 V GND 200 Ω VDD 10 pF 0.15 V tPZL VOH - 0.15 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VCC/2 VCC/2 Output Control (VIN) V /2 DD VDD VOH VOL + 0.15 V VOH VOL 0 V VDD/2 tPZH tPLZ tPHZ Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 VCC (see Note B) VOL VO VSEL VO TS2PCIE412 SCDS269C – MARCH 2009 – REVISED APRIL 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION (Enable and Disable Times) A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. Figure 6. Test Circuit and Voltage Waveforms 8 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TS2PCIE412 |
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