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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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ISL267450 Fiches technique(PDF) 7 Page - Intersil Corporation |
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ISL267450 Fiches technique(HTML) 7 Page - Intersil Corporation |
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7 / 19 page  ISL267450 7 FN8341.0 August 10, 2012 IDD Positive Supply Input Current Static VDD = 3V/5V; SCLK ON or OFF 1 µA Dynamic VDD = 5V; fS = 1MSPS 1.7 mA VDD = 3V; fS = 833kSPS 1.25 mA PD Power Dissipation Static Mode VDD = 3V/5V; SCLK ON or OFF 5 µW Dynamic VDD = 5V; fS = 1MSPS 8.5 mW VDD = 3V; fS = 833kSPS 3.75 mW NOTES: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 7. The absolute voltage applied to each analog input must not exceed VDD. 8. Read about “Acquisition Time” on page 14 for a discussion of this parameter. Electrical Specifications VDD = +3.0V to +3.3V, FSCLK = 15MHz, FS = 833kSPS, VREF = 1.25V, FIN = 200kHz; VDD = +4.75V to +5.25V, FSCLK = 18MHz, FS =1MSPS, VREF = 2.5V, FIN = 300kHz; VCM = VREF, TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS Electrical Specifications Limits established by characterization and are not production tested. VDD = +4.75V to +5.25V, FSCLK = 18MHz, FS =1MSPS, VREF = 2.5V, FIN = 300kHz; VCM = VREF, TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS fSCLK Clock Frequency 0.05 18 MHz tSCLK Clock Period 55 ns tCONVERT Conversion Time 16 x tSCLK 888 ns tQUIET Quiet Time Before Sample 25 ns tCSS CS Falling Edge to SCLK Falling Edge Setup Time 10 ns tDISABLE CS Falling Edge to SDATA Disable Time (Note 9) Extrapolated back to true bus relinquish 10 35 ns Data Access Time after SCLK Falling Edge tSWH SCLK High Pulsewidth 0.4 x tSCLK 0.6 x tSCLK ns tSWL SCLK Low Pulsewidth 0.4 x tSCLK 0.6 x tSCLK ns tCLKDV SCLK Falling Edge to SDATA Valid 40 ns tSDH SCLK Falling Edge to SDATA Hold 10 ns tACQ Acquisition Time (Note 8) ns tCSW CS Pulse Width 10 ns tCDV CS Falling Edge to SDATA Valid 20 ns Electrical Specifications Limits established by characterization and are not production tested. VDD = +3.0V to +3.3V, FSCLK = 15MHz, FS = 833kSPS, VREF = 1.25V, FIN = 200kHz; VREF = 2.5V; VCM = VREF, TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS fSCLK Clock Frequency 0.05 15 MHz tSCLK Clock Period 55 ns tCONVERT Conversion Time 16 x tSCLK 1.07 µs |
Numéro de pièce similaire - ISL267450 |
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Description similaire - ISL267450 |
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