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TPS3898PDRYT Fiches technique(PDF) 11 Page - Texas Instruments |
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TPS3898PDRYT Fiches technique(HTML) 11 Page - Texas Instruments |
11 / 21 page GND VCC ENABLE SENSE SENSE_OUT GPIO GND TPS3897 DSP, CPU, or FPGA VCC1 R1 R2 V IN CT R P 0.1 F m TPS3895, TPS3896 TPS3897, TPS3898 www.ti.com SBVS172A – JULY 2011 – REVISED SEPTEMBER 2011 OUTPUT PIN (SENSE_OUT) In a typical TPS389x application, the SENSE_OUT or SENSE_OUT outputs are connected to a reset/enable input of the processor (DSP, CPU, FPGA, ASIC, etc.) or connected to the enable input of a voltage regulator. The TPS3897 and TPS3898 provide open-drain outputs. Pull-up resistors must be used to hold these lines high when SENSE_OUT is asserted or SENSE_OUT is not asserted. By connecting the pull-up resistors to the proper voltage rails, SENSE_OUT or SENSE_OUT can be connected to other devices at the correct interface voltage levels. The outputs can be pulled up to 18 V independent of the supply voltage (VCC). To ensure proper voltage levels, some thought should be given to choosing the correct pull-up resistor values. The ability to sink current is determined by the supply voltage; therefore, if VCC = 5 V and the desired output pull-up is 18V, then to obtain a sink current of 1 mA or less (as mentioned in Electrical Characteristics), the pull-up resistor value should be greater than 18 k Ω . By using wired-OR logic, any combination of SENSE_OUT can be merged into one logic signal. The TPS3895 and TPS3896 provide push-pull outputs. The logic high level of the outputs is determined by the VCC pin voltage. With this configuration, pull-up resistors are not required and some board area can be saved. However, all the interface logic levels should be examined. All the SENSE_OUT and SENSE_OUT connections must be compatible with the VCC pin logic level. The SENSE_OUT or SENSE_OUT outputs are defined for a VCC voltage higher than 0.8 V. Table 2 and Table 3 are truth tables that describe how the outputs are asserted or de-asserted. When the conditions are met, the device changes state from de-asserted to asserted after a preconfigured delay time. However, the transitions from asserted to de-asserted are performed almost immediately with minimal propagation delay of 16 µs (typ). Figure 1 to Figure 4 show the timing diagrams and describe the relationship between the threshold voltages (VIT+ and Vhys), enable inputs, and respective outputs. INPUT PIN (SENSE) The SENSE input pin allows any system voltage above 0.5 V to be monitored. If the voltage at the SENSE pin exceeds VIT+, and provided that the enable pin is asserted (ENABLE = high or ENABLE = low), then the output is asserted after the capacitor-adjustable delay time elapses. When the voltage at the SENSE pin drops below (VIT+ – Vhys), then the output is de-asserted. The comparator has a built-in hysteresis to ensure smooth output assertions and de-assertions. Although not required in most cases, for extremely noisy applications, it is good analog design practice to place a 1-nF to 10-nF bypass capacitor at the SENSE input in order to reduce sensitivity to transients and layout parasitics. The TPS389x family monitor the voltage at SENSE with the use of external resistor divider, as shown in Figure 23. Figure 23. Using TPS3897 to Monitor User-Defined Threshold Voltage The target threshold voltage can be calculated by using Equation 1: VTARGET = (1+R1/R2) × 0.5 (V) (1) Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): TPS3895 TPS3896 TPS3897 TPS3898 |
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