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TPS5130-Q1 Fiches technique(PDF) 7 Page - Texas Instruments

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No de pièce TPS5130-Q1
Description  TRIPLE SYNCHRONOUS BUCK CONTROLLER WITH NMOS LDO CONTROLLER
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

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TPS5130-Q1
www.ti.com................................................................................................................................................................................................... SLVS866 – MARCH 2009
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
CT
7
I/O
External capacitor from CT to GND adjusts frequency of the triangle oscillator.
FB1
1
O
Feedback output of SBRC-CH1 error amplifier
FB2
4
O
Feedback output of SBRC-CH2 error amplifier
FB3
14
O
Feedback output of SBRC-CH3 error amplifier
Fault latch timer pin. An external capacitor connected between FLT and GND sets FLT enable time
FLT
47
I/O
up.
GND
8
Signal GND
Inverting input of SBRC-CH1 error amplifier, skip comparator, OVP1/UVP1 comparator, and PG
INV1
48
I
comparator
Inverting input of SBRC-CH2 error amplifier, skip comparator, OVP2/UVP2 comparator, and PG
INV2
3
I
comparator
Inverting input of SBRC-CH3 error amplifier, skip comparator, OVP3/UVP3 comparator, and PG
INV3
15
I
comparator
INV_LDO
25
I
Inverting input of LDO error amplifier, OVP/UVP comparators, and PG comparator
LDO_CUR
28
I
Current sense input of LDO regulator
LDO_GATE
27
O
Gate control output of external MOSFET for LDO regulator
LDO regulator output. If output voltage has an overshoot when output current changes high to low
LDO_OUT
26
I/O
quickly, it absorbs electrical charge from this pin.
LDO_IN
29
I
Supply voltage input and current sense input of LDO regulator
LH1
46
I/O
Bootstrap capacitor connection for SBRC-CH1 high-side gate driver
LH2
34
I/O
Bootstrap capacitor connection for SBRC-CH2 high-side gate driver
LH3
20
I/O
Bootstrap capacitor connection for SBRC-CH3 high-side gate driver
SBRC-CH1 high-side gate driving return. Connect this pin to the junction of the high-side and
LL1
44
I/O
low-side MOSFETs for floating drive configuration. This pin is also an input terminal for current
comparator.
SBRC-CH2 high-side gate driving return. Connect this pin to the junction of the high-side and
LL2
36
I/O
low-side MOSFETs for floating drive configuration. This pin is also an input terminal for current
comparator.
SBRC-CH3 high-side gate driving return. Connect this pin to the junction of the high-side and
LL3
22
I/O
low-side MOSFETs for floating drive configuration. This pin is also an input terminal for current
comparator.
OUT1_d
43
O
Gate drive output for SBRC-CH1 low-side MOSFETs
OUT2_d
37
O
Gate drive output for SBRC-CH2 low-side MOSFETs
OUT3_d
23
O
Gate drive output for SBRC-CH3 low-side MOSFETs
OUT1_u
45
O
Gate drive output for SBRC-CH1 high-side MOSFETs
OUT2_u
35
O
Gate drive output for SBRC-CH2 high-side MOSFETs
OUT3_u
21
O
Gate drive output for SBRC-CH3 high-side MOSFETs
Ground for SBRC-CH1 MOSFETs drivers. It is connected to the current limiting comparator's
OUTGND1
42
O
negative input.
Ground for SBRC-CH2 MOSFETs drivers. It is connected to the current limiting comparator's
OUTGND2
38
O
negative input.
Ground for SBRC-CH3 MOSFETs drivers. It is connected to the current limiting comparator's
OUTGND3
24
O
negative input.
Power good open-drain output. PG comparators monitor all SBRCs and LDOs overvoltage and
PGOUT
16
O
undervoltage status. The threshold is ±7%. When one of the outputs is beyond this condition,
PGOUT goes low.
Programmable delay for PGOUT. Connect an external capacitor between this pin and GND to
PG_DELAY
17
I/O
specify time delay.
PWM or auto PWM/SKIP mode select
PWM_SEL
6
I
H= Auto PWM/SKIP
L = PWM fixed
Copyright © 2009, Texas Instruments Incorporated
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