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74ALVCF162834GRE4 Fiches technique(PDF) 1 Page - Texas Instruments |
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74ALVCF162834GRE4 Fiches technique(HTML) 1 Page - Texas Instruments |
1 / 14 page www.ti.com FEATURES DESCRIPTION/ORDERING INFORMATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 NC NC Y1 GND Y2 Y3 VCC Y4 Y5 Y6 GND Y7 Y8 Y9 Y10 Y11 Y12 GND Y13 Y14 Y15 VCC Y16 Y17 GND Y18 OE LE GND NC A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 CLK GND DGG, DGV, OR DL PACKAGE (TOP VIEW) NC − No internal connection SN74ALVCF162834 3.3-V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES409B – AUGUST 2002 – REVISED OCTOBER 2004 • Member of the Texas Instruments Widebus™ Family • Ideal for Use in PC133 Register DIMM • Typical Output Skew . . . <250 ps • VCC = 3.3 V ± 0.3 V . . . Normal Range • VCC = 2.7 V to 3.6 V . . . Extended Range • VCC = 2.5 V ± 0.2 V • Rail-to-Rail Output Swing for Increased Noise Margin • Balanced Output Drivers . . . ±18 mA • Low Switching Noise • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) This 18-bit universal bus driver is designed for 2.3-V to 3.6-V VCC operation. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. The ALVCF162834 has series damping resistors in the device output structure that reduce switching noise in 128-MB and 256-MB SDRAM modules. Designed with a drive capability of ±18 mA, this device is a midway drive between the ALVC162834 ( ±12 mA) and ALVC16834 (±24 mA). The SN74ALVCF162834 is a faster version of the SN74ALVC162834. It is suitable for PC133 applications, particularly for SDRAM modules clocked at 133 MHz. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION TA PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING Tube SN74ALVCF162834DL SSOP - DL ALVCF162834 Tape and reel SN74ALVCF162834DLR -40 °C to 85°C TSSOP - DGG Tape and reel SN74ALVCF162834GR ALVCF162834 TVSOP - DGV Tape and reel SN74ALVCF162834VR VF162834 (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 2002–2004, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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