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TPS27081ADDCR Fiches technique(PDF) 5 Page - Texas Instruments |
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TPS27081ADDCR Fiches technique(HTML) 5 Page - Texas Instruments |
5 / 14 page rise 2 3 3.9 R2 C1 t sec VIN ´ ´ = final initial inrush load load VOUT VOUT I C C Vout Slew Rate dv dt - = ´ = ´ Q1 R2 VGS VIN V R1 R2 = ´ + VIN VOUT R1/C1 ON/OFF Q1 Q2 R1 C1 ESD ESD ESD ESD R2 CL (2, 3) R2 (1) (5) (6) (4) GPIO/ Logic Up to 8V Supply LOAD TPS27081A www.ti.com SLVSBE9A – APRIL 2012 – REVISED JULY 2012 APPLICATION INFORMATION The TPS27081A IC is a high side load switch that integrates a Power PFET and a Control NMOS in a tiny package. The TPS27081A internal components are rated for up to 8V supply and support up to 3A of load current.The TPS27081A can be used in a variety applications. Figure 3 below shows a general application of TPS27081A to control the load inrush current. Figure 3. Typical Application Diagram Configuring Q1 ON Resistance The VGS-Q1 Gate-Source voltage across the PMOS transistor Q1 sets its ON resistance RDSQ1(ON). Directly connecting the pin R2 to ground maximizes the ON state VGS-Q1 and thus minimizes the VIN to VOUT voltage dropout. When a resistor R2 is installed to control the Turn-ON slew rate then VGS-Q1 is given by: e.g. R1= 10 x R2, VIN = 5V sets VGS-Q1 = 4.5V (1) Note: It is recommended to keep R1 > 20 x R2; while limiting maximum value of resistor R1 to approximately 2M Ω Configuring Turn-ON Slew Rate Switching a large capacitive load CL instantaneously results in a load inrush current given by the following equation: (2) An uncontrolled fast rising ON/OFF logic input may result in a high slew rate at the output resulting in a very high dv/dt thus leading to a higher inrush current. To control the inrush current connect a resistor R2 and a capacitor C1 as shown in the Figure 3. Use the following equation to configure the TPS27081A slew rate to a specific value. Refer to Table 1 for component values to configure TPS27081A to achieve standard slew rates. (3) Where trise is the time delta starting from the ON/OFF signal’s rising edge to charge up the load capacitor CL from 10% to 90% of VIN voltage. Note: The trise equation is accurate to within +/-20% across full VIN range supported by TPS27081A. Ensure that R1 > 10xR2. Table 1. Component Values for VOUT Rise Time Rise Time (sec) VIN (V) R2 ( Ω) C1 (µF) CL (µF)(1) 250n 5.0 0 (short) 0 (open) 0 (open) 100µ 5.0 6.65k 0.01 10.0µ 200µ 1.2 5.23k 0.01 10.0µ 470µ 5.0 3.30k 0.12 10.0µ (1) Component values for VOUT rise time Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): TPS27081A |
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