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TL034CDR Fiches technique(PDF) 8 Page - Texas Instruments |
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TL034CDR Fiches technique(HTML) 8 Page - Texas Instruments |
8 / 72 page TL03x, TL03xA ENHANCED-JFET LOW-POWER LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS180C − FEBRUARY 1997 − REVISED DECEMBER 2001 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL031I and TL031AI electrical characteristics at specified free-air temperature TL031I, TL031AI PARAMETER TEST CONDITIONS TA VCC± = ±5 V VCC± = ±15 V UNIT PARAMETER TEST CONDITIONS TA MIN TYP MAX MIN TYP MAX UNIT TL031I 25 °C 0.54 3.5 0.5 1.5 V Input offset voltage VO = 0, V 0 TL031I Full range† 5.3 3.3 mV VIO Input offset voltage VIC = 0, RS = 50 Ω TL031AI 25 °C 0.41 2.8 0.34 0.8 mV RS = 50 Ω TL031AI Full range† 4.6 2.6 TL031I 25 °C to 65 62 a Temperature coefficient f VO = 0, V 0 TL031I 25 C to 85 °C 6.5 6.2 V/ °C a V IO of input offset voltage VIC = 0, RS = 50 Ω TL031AI 25 °C to 65 62 25 μV/°C input offset voltage RS = 50 Ω TL031AI 25 C to 85 °C 6.5 6.2 25 Input offset voltage VO = 0, V 0 25 °C 004 004 V/mo Input offset voltage long-term drift‡ VIC = 0, RS = 50 Ω 25 °C 0.04 0.04 μV/mo I Input offset current VO = 0, VIC = 0 25 °C 1 100 1 100 pA IIO Input offset current VO = 0, VIC = 0 See Figure 5 85 °C 0.02 0.45 0.02 0.45 nA I Input bias current VO = 0, VIC = 0 25 °C 2 200 2 200 pA IIB Input bias current VO = 0, VIC = 0 See Figure 5 85 °C 0.2 0.9 0.2 0.9 nA V Common-mode input 25 °C −1.5 to 4 −3.4 to 5.4 −11.5 to 14 −13.4 to 15.4 V VICR Common mode input voltage range Full range† −1.5 to 4 −11.5 to 14 V M i iti k 25 °C 3 4.3 13 14 VOM+ Maximum positive peak output voltage swing RL = 10 kΩ −40 °C 3 4.1 13 14 V VOM+ output voltage swing RL 10 k Ω 85 °C 3 4.4 13 14 V Mi ti k 25 °C −3 −4.2 −12.5 −13.9 VOM− Maximum negative peak output voltage swing RL = 10 kΩ −40 °C −3 −4.1 −12.5 −13.8 V VOM− output voltage swing RL 10 k Ω 85 °C −3 −4.2 −12.5 −14 V 25 °C 4 12 5 14.3 AVD Large-signal differential voltage amplification§ RL = 10 kΩ −40 °C 3 8.4 4 11.6 V/mV AVD voltage amplification§ RL 10 k Ω 85 °C 4 13.5 5 15.3 V/mV ri Input resistance 25 °C 1012 1012 Ω ci Input capacitance 25 °C 5 4 pF Cd V V i 25 °C 70 87 75 94 CMRR Common-mode rejection ratio VIC = VICRmin, VO =0 RS =50 Ω −40 °C 70 87 75 94 dB CMRR rejection ratio VO = 0, RS = 50 Ω 85 °C 70 87 75 94 dB Supply-voltage 25 °C 75 96 75 96 kSVR Supply-voltage rejection ratio VO = 0, RS = 50 Ω −40 °C 75 96 75 96 dB SVR rejection ratio ( ΔVCC±/ΔVIO) O , S 85 °C 75 96 75 96 † Full range is −40 °C to 85°C. ‡ Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV. § At VCC± = ±5 V, VO = ±2.3 V; at VCC± = ±15 V, VO = ±10 V |
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