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TCA9548ARGER Fiches technique(PDF) 5 Page - Texas Instruments |
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TCA9548ARGER Fiches technique(HTML) 5 Page - Texas Instruments |
5 / 22 page 1 1 1 0 A1 A2 A0 Slave Address R/W Fixed Hardware Selectable TCA9548A www.ti.com SCPS207A – MAY 2012 – REVISED JULY 2012 Figure 4. TCA9548A Address Table 1. Address Reference INPUTS I2C BUS SLAVE ADDRESS A2 A1 A0 L L L 112 (decimal), 70 (hexadecimal) L L H 113 (decimal), 71 (hexadecimal) L H L 114 (decimal), 72 (hexadecimal) L H H 115 (decimal), 73 (hexadecimal) H L L 116 (decimal), 74 (hexadecimal) H L H 117 (decimal), 75 (hexadecimal) H H L 118 (decimal), 76 (hexadecimal) H H H 119 (decimal), 77 (hexadecimal) The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read is selected, while a low (0) selects a write operation. Control Register Following the successful acknowledgment of the address byte, the bus master sends a command byte that is stored in the control register in the TCA9548A (see Figure 5). This register can be written and read via the I2C bus. Each bit in the command byte corresponds to a SCn/SDn channel and a high (or 1) selects this channel. Multiple SCn/SDn channels may be selected at the same time. When a channel is selected, the channel becomes active after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn lines are in a high state when the channel is made active, so that no false conditions are generated at the time of connection. A stop condition always must occur immediately after the acknowledge cycle. If multiple bytes are received by the TCA9548A, it saves the last byte received. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): TCA9548A |
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