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FAN302UL Fiches technique(PDF) 6 Page - Fairchild Semiconductor |
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FAN302UL Fiches technique(HTML) 6 Page - Fairchild Semiconductor |
6 / 19 page © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN302UL • Rev. 1.0.3 6 Electrical Characteristics (Continued) VDD=15V and TA=25 °C unless noted. Symbol Parameter Condition Min. Typ. Max. Unit Voltage-Sense Section ITC Bias Current VCS=5V 8.75 10.00 11.25 μA VVS-CM-MIN VS Sampling Voltage to Switch to the Second Pulse-by-Pulse Current Limit in Power Limit Mode (6) 0.55 V VVS-CM-MAX VS Sampling Voltage to Switch Back to the Normal Pulse-by-Pulse Current Limit (6) 0.75 V VSN-CC VS Sampling Voltage to Start Frequency Decreasing in CC Mode VCS=5V, fS1=fOSC-2KHz 2.15 V VSG-CC VS Sampling Voltage to End Frequency Decreasing in CC Mode VCS=5V, fS2=fOSC-CCM +2KHz 0.70 V SG-CC Frequency Decreasing Slope of CC Regulation SG-CC= (fS1-fS2) /(VSN-CC-VSG-CC) 52 64 76 kHz/V IVS-UVP Sinking Current Threshold for Brownout Protection (6) 47 μA VVS-OFFSET ZCD Comparator Internal Offset Voltage (6) 200 mV VVS-OVP Output Over-Voltage Protection with VS Sampling Voltage 2.80 2.85 V tVS-OVP Output Over-Voltage Protection Debounce Time f=140kHz 60 120 μs Current-Sense Section VVR Internal Reference Voltage for CC Regulation 2.475 2.500 2.525 V VCCR Variation Test Voltage on CS Pin for CC Output (Non-Inverting Input of Error Amplifier for CC Regulation) VCS=0.41V 2.405 2.430 2.455 V VSTH Normal Current Limit Threshold Voltage 0.7 V VSTH-VA Second Current Limit Threshold Voltage at Power Limit Mode (Vs<VVS-CM-MAX) VVS=0.3V 0.25 0.30 0.35 V tPD GATE Output Turn-Off Delay 100 150 ns tMIN Minimum On Time VCS=5V, VVS=2.5, VFB=5V (Test Mode) 180 250 320 ns tLEB Leading-Edge Blanking Time (6) 100 150 200 ns VSLOPE Slope Compensation (6) Maximum Duty Cycle 0.3 V GATE Section DCYMAX Maximum Duty Cycle 61 64 67 % VGATE-L Output Voltage Low VDD=25V, IO=10mA 1.5 V VGATE-H Output Voltage High VDD=8V, IO=1mA 5 8 V VGATE-H Output Voltage High VDD=5.5V, IO=1mA 4.0 5.5 V tr Rising Time VDD=15V, CL=1nF 100 140 180 ns tf Falling Time VDD=15V, CL=1nF 30 50 70 ns VGATE- CLAMP Gate Output Clamping Voltage VDD=25V 13 15 17 V Notes: 4. fOSC-CM-MIN occurs when the power unit enters CCM operation. 5. AV is a scale-down ratio of the internal voltage divider of the FB pin. 6. Not tested; guaranteed by design. |
Numéro de pièce similaire - FAN302UL |
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Description similaire - FAN302UL |
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