CDCV304TPWREP datasheet(3/13 Pages) TI1

No de pièce	CDCV304TPWREP

Description	200-MHz GENERAL-PURPOSE CLOCK BUFFER, PCI-X COMPLIANT

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CDCV304-EP

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SCAS927A – MARCH 2012

THERMAL INFORMATION

CDCV304

THERMAL METRIC(1)

PW

UNITS

8 PINS

θJA

Junction-to-ambient thermal resistance(2)

175.8

θJCtop

Junction-to-case (top) thermal resistance(3)

61.8

θJB

Junction-to-board thermal resistance(4)

104.3

°C/W

ψJT

Junction-to-top characterization parameter(5)

7.7

ψJB

Junction-to-board characterization parameter(6)

102.6

xxx

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5)

The junction-to-top characterization parameter,

ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining

θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6)

The junction-to-board characterization parameter,

ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining

θJA , using a procedure described in JESD51-2a (sections 6 and 7).

RECOMMENDED OPERATING CONDITIONS

MIN

NOM

MAX

UNIT

Supply voltage, VDD

2.3

3.6

V

Low-level input voltage, VIL

0.3 x VDD

V

High-level input voltage, VIH

0.7 x VDD

V

Input voltage, VI

0

VDD

V

VDD = 2.5 V

–12

High-level output current, IOH

mA

VDD = 3.3 V

–24

VDD = 2.5 V

12

Low-level output current, IOL

mA

VDD = 3.3 V

24

Operating free-air temperature, TA

–40

105

°C

TIMING REQUIREMENTS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fclk

Clock frequency

0

200

MHz

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