ADF4360-9BCPZRL datasheet(5/24 Pages) AD

No de pièce	ADF4360-9BCPZRL

Description	Clock Generator PLL with Integrated VCO

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Data Sheet

ADF4360-9

Rev. B | Page 5 of 24

TIMING CHARACTERISTICS1

AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless otherwise noted.

Table 2.

Parameter

Limit at TMIN to TMAX (B Version)

Unit

Test Conditions/Comments

t1

20

ns min

LE setup time

t2

10

ns min

DATA to CLK setup time

t3

10

ns min

DATA to CLK hold time

t4

25

ns min

CLK high duration

t5

25

ns min

CLK low duration

t6

10

ns min

CLK to LE setup time

t7

20

ns min

LE pulse width

1 Refer to the

section for the recommended power-up procedure for this device.

Power-Up

CLK

DATA

LE

DB23 (MSB)

DB22

DB2

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t1

t2

t3

t7

t6

t4

t5

Figure 2. Timing Diagram

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