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DAC2932 Fiches technique(PDF) 3 Page - Texas Instruments |
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DAC2932 Fiches technique(HTML) 3 Page - Texas Instruments |
3 / 29 page DAC2932 SBAS279D − AUGUST 2003 − REVISED JULY 2005 www.ti.com 3 ELECTRICAL CHARACTERISTICS: I-DAC At TA = TMIN to TMAX (typical values are at TA = 25°C), +VA = +3V, +VD = +3V, Update Rate = 40MSPS, IOUTFS = 2mA, RL = 250Ω, CL ≤ 10pF, GSET = H, and internal reference, unless otherwise noted. DAC2932 PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Resolution 12 Bits Output update rate (fCLOCK) 40 MSPS Specified temperature range, operating Ambient, TA −40 +85 °C Static Accuracy(1)(2) Differential nonlinearity (DNL) −3.5 ±0.5 +3.5 LSB Integral nonlinearity (INL) −8 ±1.5 +8 LSB Dynamic Performance(3) Spurious-free dynamic range (SFDR) To Nyquist, 0dBFS fOUT = 0.2MHz, fCLOCK = 20MSPS 68 dBc fOUT = 0.55MHz, fCLOCK = 40MSPS 71 dBc fOUT = 1MHz, fCLOCK = 25MSPS(4) 58 70 dBc fOUT = 2.2MHz, fCLOCK = 40MSPS 72 dBc fOUT = 5MHz, fCLOCK = 40MSPS 75 dBc fOUT = 10MHz, fCLOCK = 40MSPS 69 dBc fOUT = 20MHz, fCLOCK = 40MSPS 57 dBc Spurious-free dynamic range within a window fOUT = 2.2MHz, fCLOCK = 40MSPS 1MHz span 76 dBc fOUT = 10MHz, fCLOCK = 40MSPS 2MHz span 74 dBc Total harmonic distortion (THD) fOUT = 0.55MHz, fCLOCK = 40MSPS −70 dBc fOUT = 1MHz, fCLOCK = 25MSPS(4) −58 −69 dBc fOUT = 2.2MHz, fCLOCK = 40MSPS −70 dBc Signal-to-noise and distortion (SINAD) fOUT = 1MHz, fCLOCK = 25MSPS(4) 52 61 dBc Output settling time(1) to 0.1% 20 ns Output rise time(1) 10% to 90% 7.7 ns Output fall time(1) 10% to 90% 7.4 ns DC Accuracy Full-scale output range(5)(6) (FSR) All bits high, IOUT1, IOUT2 0.5 2 mA Output compliance range(7), VCO −0.5 +0.5 +0.8 V Gain error (Full-Scale) −2 ±0.5 +2 %FSR Gain error drift 70 ppmFSR/°C Gain matching −2.5 +0.6 +2.5 %FSR Offset error ±0.001 %FSR Power-supply rejection, +VA +3V, ±10%, at 25°C −0.9 +0.5 +0.9 %FSR/V Power-supply rejection, +VD +3V, ±10%, at 25°C −0.12 +0.03 +0.12 %FSR/V Output resistance 200 kΩ Output capacitance IOUT, IOUT to Ground 5 pF (1) At output IOUT1, IOUT2, while driving a 250Ω load, transition from 000h to FFFh. (2) Measured at fCLOCK = 25MSPS and fOUT = 1.0MHz. (3) Differential, transformer (n = 4:1) coupled output, RL = 400Ω. (4) Differential outputs with a 250Ω load. (5) Nominal full−scale output current is I OUTFS + 32 IREF + 32 VREF R SET ; with VREF + 1.22V (typ) and RSET + 19.6kW (1%) (6) Ensured by design and characterization; not production tested. (7) Gain error to remain ≤10% FSR over the full compliance range. (8) Combined power dissipation of I-DAC and V-DAC. |
Numéro de pièce similaire - DAC2932 |
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Description similaire - DAC2932 |
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