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TPS51640ARSLT Fiches technique(PDF) 11 Page - Texas Instruments

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No de pièce TPS51640ARSLT
Description  Dual-Channel (3-Phase CPU/1-Phase GPU) SVID, D-CAP??Step-Down Controller for
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

TPS51640ARSLT Fiches technique(HTML) 11 Page - Texas Instruments

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TPS51640A, TPS59640, TPS59641
www.ti.com
SLUSAQ2
– JANUARY 2012
PIN
I/O
DESCRIPTION
NAME
NO.
Voltage divider to VREF. A resistor to GND sets the operating frequency of the CPU converter. The voltage level
CF-IMAX
13
I
sets the maximum operating current of the CPU converter. The IMAX value is an 8-bit A/D where VIMAX = VREF ×
IMAX / 255. Both are latched at start-up.
Voltage sense return tied for the CPU converter. Tie to GND with a 10-
Ω resistor to close feedback when the
CGFB
12
I
microprocessor is not in the socket.
Analog current monitor output for the CPU converter. VCIMON = ΣVCS × ACS × (1 + RCIMON/RCOCP). Connect a
CIMON
3
O
220-nF capacitor to GND for stability.
Resistor to GND (RCOCP) selects 1 of 8 OCP levels (per phase, latched at start-up) of the CPU converter. Also,
COCP-I
2
I
voltage divider to CIMON. Resistor ratio sets the IMON gain (see CIMON pin description).
CPGOOD
17
O
IMVP-7_PWRGD output for the CPU converter. Open-drain.
CSW1
45
I/O
Top N-channel FET gate drive return for CPU phase 1.
CSW2
40
I/O
Top N-channel FET gate drive return for CPU phase 2.
CPWM3
36
O
PWM control for the external driver, 5V logic level.
Skip mode control of the external driver for the CPU converter. A logic HI = FCCM, LO = SKIP. R to GND selects
CSKIP
35
O
1 of 8 OSR/USR levels. 0.1 V
< VCSKIP < 0.3 V at start-up turns OSR off.
Thermal sensor connection for the CPU converter. A resistor connected to VREF forms a divider with an NTC
CTHERM
1
I/O
thermistor connected to GND.
Voltage sense line tied directly to VCORE of the CPU converter. Tie to VCORE with a 10-Ω resistor to close
CVFB
11
I
feedback when
µP is not in the socket. The soft-stop transistor is on this pin
Negative current sense input for the GPU converter. Connect to the most negative node of current sense resistor
GCSN
28
I
or inductor DCR sense network. GCSN has a secondary OVP comparator and includes the soft-stop pull-down
transistor.
Positive current sense input for the GPU converter. Connect to the most positive node of current sense resistor
GCSP
29
I
or inductor DCR sense network. Tie to V3R3 to disable the GPU converter.
GCOMP
27
O
Output of gM error amplifier for the GPU converter. A resistor to VREF sets the droop gain.
Voltage sense return tied for the GPU converter. Tie to GND with a 10-
Ω resistor to close feedback when the
GGFB
25
I
microprocessor is not in the socket.
24
I
Voltage divider to VREF. R to GND sets the operating frequency of the GPU converter. The voltage level sets
GF-IMAX
the maximum operating current of the GPU converter. The IMAX value is an 8-bit A/D where VIMAX = VREF ×
IMAX / 255. Both are latched at start-up.
30
O
Analog current monitor output for the GPU converter. VGIMON = VISENSE × (1 + RGIMON/RGOCP). Connect a
GIMON
220-nF capacitor to GND for stability.
31
I
Voltage divider to GIMON. Resistor ratio sets the IMON gain (see GIMON pin). Resistor to GND (RGOCP) selects
GOCP-I
1 of 8 OCP levels (per phase, latched at start-up) of the GPU converter.
GPGOOD
23
O
IMVP-7_PWRGD output for the GPU converter. Open-drain.
GPWM
34
O
PWM control for the external driver, 5-V logic level.
33
O
Skip mode control of the external driver for the GPU converter, 5-V logic level. Logic HI = FCCM, LO = SKIP. R
GSKIP
to GND selects 1 of 8 OSR/USR levels. 0.1 V
< V
GSKIP< 0.3 V at start-up turns OSR off.
32
I/O
Thermal sensor input for the GPU converter. A resistor connected to VREF forms a divider with an NTC
GTHERM
thermistor connected to GND.
26
I
Voltage sense line tied directly to VGFX of the GPU converter. Tie to VGFX with a 10-Ω resistor to close feedback
GVFB
when the microprocessor is not in the socket. The soft-stop transistor is on this pin
PGND
42
Synchronous N-channel FET gate drive return.
22
I
The voltage at start-up sets 1 of 7 slew rates for both converters. The SLOW rate is SLEWRATE/4. Soft-start
SLEWA
and soft-stop rates are SLEWRATE/8. This value is latched at start-up. Tie to GND to disable SCLK timer.
48
I
5-V power input for analog circuits; connect through resistor to 5-V plane and bypass to GND with
≥1 µF ceramic
V5
capacitor
43
I
Power input for the gate drivers; connected with an external resistor to V5F; decouple with a
≥2.2 µF ceramic
V5DRV
capacitor.
V3R3
15
I
3.3-V power input; bypass to GND with
≥1 µF ceramic cap.
37
I
Provides VBAT information to the on-time circuits for both converters. A 10-k
Ω series resistor protects the
VBAT
adjacent pins from inadvertent shorts due to solder bridges or mis-probing during test.
VCLK
18
I
SVID clock. 1-V logic level.
VDIO
20
I/O
SVID digital I/O line. 1-V logic level.
VREF
14
O
1.7-V, 500-
µA reference. Bypass to GND with a 0.22-µF ceramic capacitor.
Copyright
© 2012, Texas Instruments Incorporated
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